| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 48 INSTRUCTION(FPTrunc, 1, 1, experimental_constrained_fptrunc, FP_ROUND)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 599 FP_ROUND, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 104 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; in SoftenFloatResult()
779 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; in SoftenFloatOperand()
824 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
988 Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), in SoftenFloatOp_STORE()
1661 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break; in ExpandFloatOperand()
1761 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ExpandFloatOp_FP_ROUND()
2142 case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break; in PromoteFloatResult()
2376 DAG.getNode(ISD::FP_ROUND, DL, VT, NV, DAG.getIntPtrConstant(0, DL))); in PromoteFloatRes_XINT_TO_FP()
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| D | LegalizeVectorTypes.cpp | 54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
305 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecRes_FP_ROUND()
601 case ISD::FP_ROUND: in ScalarizeVectorOperand()
765 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecOp_FP_ROUND()
885 case ISD::FP_ROUND: in SplitVectorResult()
1710 if (N->getOpcode() == ISD::FP_ROUND) { in SplitVecRes_UnaryOp()
1934 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; in SplitVectorOperand()
2599 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
2651 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); in SplitVecOp_FP_ROUND()
2652 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); in SplitVecOp_FP_ROUND()
[all …]
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| D | LegalizeVectorOps.cpp | 435 case ISD::FP_ROUND: in LegalizeOp()
573 case ISD::FP_ROUND: in Promote()
612 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, DAG.getIntPtrConstant(0, dl)); in Promote()
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| D | LegalizeDAG.cpp | 2895 case ISD::FP_ROUND: in ExpandNode()
3231 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, in ExpandNode()
4389 TruncOp = ISD::FP_ROUND; in PromoteNode()
4398 if (TruncOp != ISD::FP_ROUND) in PromoteNode()
4458 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4481 DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4497 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4519 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
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| D | SelectionDAGDumper.cpp | 327 case ISD::FP_ROUND: return "fp_round"; in getOperationName()
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| D | DAGCombiner.cpp | 1583 case ISD::FP_ROUND: return visitFP_ROUND(N); in visit()
9428 CastOpcode == ISD::FP_ROUND) && in matchVSelectOpSizesWithSetCC()
9454 if (CastOpcode == ISD::FP_ROUND) { in matchVSelectOpSizesWithSetCC()
12786 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
12790 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1)); in visitFDIV()
12868 N1.getOpcode() == ISD::FP_ROUND)) { in CanCombineFCOPYSIGN_EXTEND_ROUND()
13225 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1); in visitFP_ROUND()
13232 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
13253 return DAG.getNode(ISD::FP_ROUND, DL, VT, N0.getOperand(0), in visitFP_ROUND()
13260 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT, in visitFP_ROUND()
[all …]
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| D | SelectionDAG.cpp | 1125 : getNode(ISD::FP_ROUND, DL, VT, Op, getIntPtrConstant(0, DL)); in getFPExtendOrRound()
4130 case ISD::FP_ROUND: { in isKnownNeverNaN()
4570 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); in getNode()
5102 if (N1CFP && Opcode == ISD::FP_ROUND) { in foldConstantFPMath()
5257 case ISD::FP_ROUND: in getNode()
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| D | TargetLowering.cpp | 5589 case ISD::FP_ROUND: in isNegatibleForFree()
5718 case ISD::FP_ROUND: in getNegatedExpression()
5719 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), in getNegatedExpression()
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| D | SelectionDAGBuilder.cpp | 325 ISD::FP_ROUND, DL, ValueVT, Val, in getCopyFromParts()
3448 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N, in visitFPTrunc()
6286 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16, in visitIntrinsicCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 161 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
166 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || in getCastInstrCost()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1717 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1745 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1746 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
3051 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 2529 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2569 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3830 case ISD::FP_ROUND: { in performFNegCombine()
3835 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3844 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
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| D | R600ISelLowering.cpp | 277 setTargetDAGCombine(ISD::FP_ROUND); in R600TargetLowering()
1849 case ISD::FP_ROUND: { in PerformDAGCombine()
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| D | SIISelLowering.cpp | 226 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in SITargetLowering()
501 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in SITargetLowering()
4074 case ISD::FP_ROUND: in LowerOperation()
7651 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag); in LowerFDIV16()
8600 case ISD::FP_ROUND: in fp16SrcZerosHighBits()
8771 case ISD::FP_ROUND: in isCanonicalized()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 819 case ISD::FP_ROUND: in PreprocessISelDAG()
833 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
1034 case ISD::FP_ROUND: in PreprocessISelDAG()
1065 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
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| D | X86TargetTransformInfo.cpp | 1338 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, in getCastInstrCost()
1436 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, in getCastInstrCost()
1517 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, in getCastInstrCost()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 936 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
937 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
999 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal); in PPCTargetLowering()
8067 Value = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
8217 FP = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
8290 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
8550 (V->getOperand(i).getOpcode() == ISD::FP_ROUND && in haveEfficientBuildVectorPattern()
12999 SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl, in combineElementTruncationToVectorTruncation()
13044 if (FirstInput.getOpcode() == ISD::FP_ROUND && in combineBVOfConsecutiveLoads()
13056 if (IsRoundOfExtLoad && N->getOperand(i).getOpcode() != ISD::FP_ROUND) in combineBVOfConsecutiveLoads()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1627 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 308 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
309 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
735 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); in AArch64TargetLowering()
2636 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl)); in LowerVectorINT_TO_FP()
2664 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
3204 case ISD::FP_ROUND: in LowerOperation()
5093 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL)); in LowerFCOPYSIGN()
5781 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0), in LowerVAARG()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 474 def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenFastISel.inc | 700 // FastEmit functions for ISD::FP_ROUND.
1706 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenFastISel.inc | 522 // FastEmit functions for ISD::FP_ROUND.
1203 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 639 setTargetDAGCombine(ISD::FP_ROUND); in SystemZTargetLowering()
6391 case ISD::FP_ROUND: return combineFP_ROUND(N, DCI); in PerformDAGCombine()
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