| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_eu.cpp | 629 { BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GFX7 | GFX75 },
630 { BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GFX7 | GFX75 },
631 { BRW_OPCODE_BFREV, 23, "bfrev", 1, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
633 { BRW_OPCODE_BFE, 24, "bfe", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
635 { BRW_OPCODE_BFI1, 25, "bfi1", 2, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
637 { BRW_OPCODE_BFI2, 26, "bfi2", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
640 { BRW_OPCODE_BRD, 33, "brd", 0, 0, GFX_GE(GFX7) },
643 { BRW_OPCODE_BRC, 35, "brc", 0, 0, GFX_GE(GFX7) },
680 { BRW_OPCODE_FBH, 75, "fbh", 1, 1, GFX_GE(GFX7) },
681 { BRW_OPCODE_FBL, 76, "fbl", 1, 1, GFX_GE(GFX7) },
[all …]
|
| D | brw_gfx_ver_enum.h | 32 GFX7 = (1 << 4), enumerator
55 case 70: return GFX7; in gfx_ver_from_devinfo()
|
| /third_party/mesa3d/src/amd/compiler/tests/ |
| D | test_to_hw_instr.cpp | 46 for (unsigned i = GFX6; i <= GFX7; i++) {
504 for (unsigned i = GFX7; i <= GFX9; i++) {
569 if (i != GFX7)
575 if (i != GFX7)
593 for (unsigned i = GFX7; i <= GFX9; i++) {
655 if (i != GFX7)
661 if (i != GFX7)
|
| D | test_tests.cpp | 56 for (int cls = GFX6; cls <= GFX7; cls++) {
|
| D | test_regalloc.cpp | 152 if (!setup_cs("v1 s1", GFX7))
170 if (!setup_cs("v2 s1", GFX7))
|
| D | test_isel.cpp | 62 for (unsigned i = GFX7; i <= GFX8; i++) {
|
| /third_party/mesa3d/src/amd/vulkan/ |
| D | si_cmd_buffer.c | 49 if (physical_device->rad_info.chip_class < GFX7) in si_write_harvested_raster_configs()
61 if (physical_device->rad_info.chip_class < GFX7) in si_write_harvested_raster_configs()
70 if (physical_device->rad_info.chip_class >= GFX7) in si_write_harvested_raster_configs()
91 if (device->physical_device->rad_info.chip_class >= GFX7) { in si_emit_compute()
174 if (physical_device->rad_info.chip_class >= GFX7) in si_set_raster_config()
221 if (physical_device->rad_info.chip_class < GFX7) in si_emit_graphics()
231 if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) { in si_emit_graphics()
326 if (physical_device->rad_info.chip_class >= GFX7) { in si_emit_graphics()
469 if (physical_device->rad_info.chip_class >= GFX7) { in si_emit_graphics()
749 if (chip_class >= GFX7) { in si_get_ia_multi_vgt_param()
[all …]
|
| D | radv_sqtt.c | 181 device->physical_device->rad_info.chip_class >= GFX7) { in radv_emit_thread_trace_start()
246 device->physical_device->rad_info.chip_class >= GFX7) { in radv_emit_thread_trace_stop()
376 family == RING_COMPUTE && device->physical_device->rad_info.chip_class >= GFX7, in radv_emit_wait_for_idle()
|
| D | radv_shader.h | 569 if (chip_class >= GFX7) { in calculate_tess_lds_size()
607 if (chip_class >= GFX7 && family != CHIP_STONEY) in get_tcs_num_patches()
|
| /third_party/mesa3d/src/amd/vulkan/winsys/null/ |
| D | radv_null_winsys.c | 95 info->chip_class = GFX7; in radv_null_winsys_query_info()
128 info->lds_encode_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4; in radv_null_winsys_query_info()
|
| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_sdma_copy_image.c | 261 (sctx->chip_class != GFX7 || in cik_sdma_copy_texture()
281 if (sctx->chip_class == GFX7) { in cik_sdma_copy_texture()
405 if (sctx->chip_class == GFX7) { in cik_sdma_copy_texture()
425 if (sctx->screen->debug_flags & DBG(NO_DMA) || sctx->chip_class < GFX7) in si_sdma_copy_image()
451 case GFX7: in si_sdma_copy_image()
|
| D | si_state_draw.cpp | 36 #define GFX(name) name##GFX7
341 if (GFX_VERSION >= GFX7) { in si_update_shaders()
413 if (GFX_VERSION < GFX7 || !mask) in si_prefetch_shaders()
693 if (sctx->chip_class >= GFX7) { in si_emit_derived_tess_state()
737 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII) in si_emit_derived_tess_state()
765 if (sctx->chip_class >= GFX7) { in si_emit_derived_tess_state()
831 if (sscreen->info.chip_class >= GFX7) { in si_get_init_multi_vgt_param()
904 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) | in si_get_init_multi_vgt_param()
1019 if (GFX_VERSION == GFX7 && in si_get_ia_multi_vgt_param()
1184 else if (GFX_VERSION >= GFX7) in si_emit_ia_multi_vgt_param()
[all …]
|
| D | si_cp_dma.c | 84 } else if (sctx->chip_class >= GFX7 && cache_policy != L2_BYPASS) { in si_emit_cp_dma()
95 } else if (sctx->chip_class >= GFX7 && cache_policy != L2_BYPASS) { in si_emit_cp_dma()
102 if (sctx->chip_class >= GFX7) { in si_emit_cp_dma()
397 assert(sctx->chip_class >= GFX7); in si_cp_dma_prefetch()
|
| D | si_fence.c | 80 if (ctx->chip_class >= GFX9 || (compute_ib && ctx->chip_class >= GFX7)) { in si_cp_release_mem()
114 if (ctx->chip_class == GFX7 || ctx->chip_class == GFX8) { in si_cp_release_mem()
152 if (screen->info.chip_class == GFX7 || screen->info.chip_class == GFX8) in si_cp_write_fence_dwords()
|
| D | si_pipe.c | 484 if (sctx->chip_class == GFX7 || sctx->chip_class == GFX8 || sctx->chip_class == GFX9) { in si_create_context()
617 case GFX7: in si_create_context()
675 if (sctx->chip_class == GFX7) { in si_create_context()
767 if (sctx->chip_class == GFX7) { in si_create_context()
1213 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 && in radeonsi_screen_create_impl()
1250 } else if (sscreen->info.chip_class >= GFX7) { in radeonsi_screen_create_impl()
1264 (sscreen->info.chip_class == GFX7 && sscreen->info.pfp_fw_version >= 211 && in radeonsi_screen_create_impl()
|
| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_winsys.c | 281 ws->info.chip_class = GFX7; in do_winsys_init()
558 if (ws->info.chip_class == GFX7) { in do_winsys_init()
584 ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != GFX7 || in do_winsys_init()
594 ws->info.has_indirect_compute_dispatch = ws->info.chip_class == GFX7 || in do_winsys_init()
598 ws->info.has_unaligned_shader_loads = ws->info.chip_class == GFX7 && in do_winsys_init()
|
| D | radeon_drm_surface.c | 60 if (info->chip_class >= GFX7) in set_micro_tile_mode()
307 if (info->chip_class >= GFX7 && num_pipes < 4) in si_compute_htile()
|
| /third_party/mesa3d/src/amd/common/ |
| D | amd_family.h | 131 GFX7, enumerator
|
| D | ac_gpu_info.c | 644 info->chip_class = GFX7; in ac_query_gpu_info()
719 info->has_sparse_vm_mappings = info->chip_class >= GFX7 && info->drm_minor >= 13; in ac_query_gpu_info()
818 info->lds_encode_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4; in ac_query_gpu_info()
849 info->has_clear_state = info->chip_class >= GFX7; in ac_query_gpu_info()
1017 info->has_gds_ordered_append = info->chip_class >= GFX7 && info->drm_minor >= 29; in ac_query_gpu_info()
1469 if (info->chip_class >= GFX7) { in ac_get_harvested_configs()
1551 if (info->chip_class >= GFX7) { in ac_get_compute_resource_limits()
|
| D | ac_rgp.c | 373 case GFX7: in ac_chip_class_to_sqtt_gfxip_level()
737 case GFX7: in ac_chip_class_to_sqtt_version()
813 case GFX7: in ac_chip_class_to_elf_gfxip_level()
|
| /third_party/mesa3d/docs/relnotes/ |
| D | 21.1.3.rst | 135 - aco: fix emitting literal offsets with SMEM on GFX7
136 - radv: do not launch an IB2 for secondary cmdbuf with INDIRECT_MULTI on GFX7
|
| D | 20.0.5.rst | 190 - radv/llvm: enable 8-bit storage features on GFX6-GFX7
193 - radv/llvm: enable 16-bit storage features on GFX6-GFX7
|
| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_assembler.cpp | 53 if (chip_class <= GFX7) in asm_context()
186 if (ctx.chip_class <= GFX7) { in emit_instruction()
387 assert(!mubuf.addr64 || ctx.chip_class <= GFX7); in emit_instruction()
388 if (ctx.chip_class == GFX6 || ctx.chip_class == GFX7) in emit_instruction()
400 if (ctx.chip_class <= GFX7 || ctx.chip_class >= GFX10) { in emit_instruction()
611 if (ctx.chip_class <= GFX7) { in emit_instruction()
|
| D | aco_reduce_assign.cpp | 137 if (program->chip_class <= GFX7) in setup_reduce_temp()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNProcessors.td | 52 // GCN GFX7 (Sea Islands (CI)).
|