Searched refs:GPR_CACHELINE_SIZE (Results 1 – 6 of 6) sorted by relevance
42 (GPR_CACHELINE_SIZE > GPR_MAX_ALIGNMENT && in ArenaStorage()43 GPR_CACHELINE_SIZE % GPR_MAX_ALIGNMENT == 0) in ArenaStorage()44 ? GPR_CACHELINE_SIZE in ArenaStorage()
63 char padding_[GPR_CACHELINE_SIZE];
147 uint8_t padding[GPR_CACHELINE_SIZE - 3 * sizeof(Atomic<intptr_t>) -
469 #define GPR_CACHELINE_SIZE (1 << GPR_CACHELINE_SIZE_LOG) macro
237 } GPR_ALIGN_STRUCT(GPR_CACHELINE_SIZE);
203 char pad[GPR_CACHELINE_SIZE];