Searched refs:HALF_SLICE_CHICKEN7 (Results 1 – 4 of 4) sorted by relevance
182 brw_load_register_imm32(brw, HALF_SLICE_CHICKEN7, in brw_upload_initial_gpu_state()
1664 #define HALF_SLICE_CHICKEN7 0xE194 macro
225 anv_batch_write_reg(&batch, GENX(HALF_SLICE_CHICKEN7), hsc7) { in init_render_queue_state()
974 iris_emit_reg(batch, GENX(HALF_SLICE_CHICKEN7), reg) { in iris_init_common_context()