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Searched refs:I915_ENGINE_CLASS_VIDEO_ENHANCE (Results 1 – 6 of 6) sorted by relevance

/third_party/mesa3d/src/intel/tools/
Daubinator_error_decode.c85 { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, "VECS_ACTHD_UDW" },
93 { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, "VECS_RING_BUFFER_CTL" },
100 { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, "VECS_FAULT_REG" },
110 [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "vecs", in ring_name_to_class()
129 { "vebox", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0 }, in ring_name_to_class()
193 case I915_ENGINE_CLASS_VIDEO_ENHANCE: in instdone_register_for_ring()
Derror2aub.c202 { "vecs", I915_ENGINE_CLASS_VIDEO_ENHANCE, true }, in engine_from_name()
208 { "vebox command stream", I915_ENGINE_CLASS_VIDEO_ENHANCE, false }, in engine_from_name()
289 } engines[I915_ENGINE_CLASS_VIDEO_ENHANCE + 1]; in main()
Daub_write.h99 } engine_setup[I915_ENGINE_CLASS_VIDEO_ENHANCE + 1];
Dintel_dump_gpu.c201 return I915_ENGINE_CLASS_VIDEO_ENHANCE; in engine_class_from_ring_flag()
/third_party/libdrm/include/drm/
Di915_drm.h122 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, enumerator
/third_party/mesa3d/include/drm-uapi/
Di915_drm.h168 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, enumerator