| /third_party/mesa3d/src/intel/isl/ |
| D | isl_drm.c | 39 return I915_TILING_NONE; in isl_tiling_to_i915_tiling()
55 return I915_TILING_NONE; in isl_tiling_to_i915_tiling()
65 case I915_TILING_NONE: in isl_tiling_from_i915_tiling()
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| /third_party/mesa3d/src/mesa/drivers/dri/i915/ |
| D | intel_blit.c | 101 if (dst_tiling != I915_TILING_NONE) { in emit_copy_blit()
105 if (src_tiling != I915_TILING_NONE) { in emit_copy_blit()
512 if (dst_tiling != I915_TILING_NONE) { in intelEmitImmediateColorExpandBlit()
542 if (dst_tiling != I915_TILING_NONE) in intelEmitImmediateColorExpandBlit()
592 pitch, src_bo, src_offset, I915_TILING_NONE, in intel_emit_linear_blit()
593 pitch, dst_bo, dst_offset, I915_TILING_NONE, in intel_emit_linear_blit()
608 pitch, src_bo, src_offset, I915_TILING_NONE, in intel_emit_linear_blit()
609 pitch, dst_bo, dst_offset, I915_TILING_NONE, in intel_emit_linear_blit()
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| D | intel_mipmap_tree.c | 137 return I915_TILING_NONE; in intel_miptree_choose_tiling()
144 return I915_TILING_NONE; in intel_miptree_choose_tiling()
149 return I915_TILING_NONE; in intel_miptree_choose_tiling()
243 if (tiling != I915_TILING_NONE) in intel_miptree_create_for_bo()
676 if (mt->region->tiling != I915_TILING_NONE) in intel_miptree_map_raw()
874 if (mt->region->tiling != I915_TILING_NONE && in intel_miptree_map()
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| D | intel_regions.c | 243 case I915_TILING_NONE: in intel_region_get_tile_masks()
273 case I915_TILING_NONE: in intel_region_get_aligned_offset()
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| D | intel_pixel_read.c | 137 dst_stride, I915_TILING_NONE); in do_blit_readpixels()
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| D | i830_texstate.c | 167 if (intelObj->mt->region->tiling != I915_TILING_NONE) { in i830_update_tex_unit()
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| D | i915_texstate.c | 182 if (intelObj->mt->region->tiling != I915_TILING_NONE) { in i915_update_tex_unit()
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| D | intel_tex_image.c | 157 src_stride, I915_TILING_NONE); in try_pbo_upload()
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| D | intel_screen.c | 462 tiling = I915_TILING_NONE; in intel_create_image()
466 tiling = I915_TILING_NONE; in intel_create_image()
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| D | i915_vtbl.c | 529 if (region->tiling != I915_TILING_NONE) { in i915_set_buf_info_for_region()
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| /third_party/libdrm/intel/ |
| D | intel_bufmgr.c | 245 *tiling_mode = I915_TILING_NONE; in drm_intel_bo_set_tiling()
256 *tiling_mode = I915_TILING_NONE; in drm_intel_bo_get_tiling()
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| D | intel_bufmgr_gem.c | 320 if (*tiling_mode == I915_TILING_NONE) in drm_intel_gem_bo_tile_size()
337 *tiling_mode = I915_TILING_NONE; in drm_intel_gem_bo_tile_size()
366 if (*tiling_mode == I915_TILING_NONE) in drm_intel_gem_bo_tile_pitch()
384 *tiling_mode = I915_TILING_NONE; in drm_intel_gem_bo_tile_pitch()
587 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) { in drm_intel_bo_gem_set_in_aperture_size()
821 bo_gem->tiling_mode = I915_TILING_NONE; in drm_intel_gem_bo_alloc_internal()
862 I915_TILING_NONE, 0, in drm_intel_gem_bo_alloc_for_render()
873 I915_TILING_NONE, 0, 0); in drm_intel_gem_bo_alloc()
904 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE) in drm_intel_gem_bo_alloc_tiled()
921 if (tiling == I915_TILING_NONE) in drm_intel_gem_bo_alloc_tiled()
[all …]
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| D | intel_bufmgr_fake.c | 848 *tiling_mode = I915_TILING_NONE; in drm_intel_fake_bo_alloc_tiled()
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| /third_party/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_bufmgr.c | 217 if (tiling == I915_TILING_NONE) in bo_tile_size()
237 if (tiling == I915_TILING_NONE) in bo_tile_pitch()
654 bo->tiling_mode = I915_TILING_NONE; in bo_alloc_internal()
709 0, I915_TILING_NONE, 0); in brw_bo_alloc()
757 if (tiling == I915_TILING_NONE) in brw_bo_alloc_tiled_2d()
1265 if (bo->tiling_mode != I915_TILING_NONE && !(flags & MAP_RAW)) in brw_bo_map()
1559 assert(tiling_mode == I915_TILING_NONE || in brw_bo_gem_create_from_prime_tiled()
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| D | brw_screen.c | 414 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR, in tiling_to_modifier()
430 if (tiling != I915_TILING_NONE && (image->offset & 0xfff)) { in brw_image_warn_if_unaligned()
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| D | brw_mipmap_tree.c | 758 BRW_MEMZONE_OTHER, I915_TILING_NONE, 0, in create_ccs_buf_for_image()
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| /third_party/mesa3d/src/gallium/drivers/crocus/ |
| D | crocus_bufmgr.c | 367 bo->tiling_mode = I915_TILING_NONE; in alloc_fresh_bo()
460 0, I915_TILING_NONE, 0); in crocus_bo_alloc()
1049 if (bo->tiling_mode != I915_TILING_NONE && !(flags & MAP_RAW)) in crocus_bo_map()
1269 bo->tiling_mode = I915_TILING_NONE; in crocus_bo_import_dmabuf()
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| D | crocus_resource.c | 771 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR, in tiling_to_modifier()
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| /third_party/mesa3d/src/intel/vulkan/ |
| D | anv_android.c | 527 case I915_TILING_NONE: in anv_image_init_from_gralloc()
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| D | anv_image.c | 1534 case I915_TILING_NONE: in resolve_ahw_image()
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| /third_party/libdrm/include/drm/ |
| D | i915_drm.h | 1231 #define I915_TILING_NONE 0 macro
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| /third_party/mesa3d/include/drm-uapi/ |
| D | i915_drm.h | 1522 #define I915_TILING_NONE 0 macro
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| /third_party/mesa3d/src/gallium/drivers/iris/ |
| D | iris_bufmgr.c | 1702 *tiling = I915_TILING_NONE; in iris_gem_get_tiling()
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| D | iris_resource.c | 1154 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR, in tiling_to_modifier()
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