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Searched refs:INVALID_REG (Results 1 – 14 of 14) sorted by relevance

/third_party/mesa3d/src/freedreno/ir3/
Dir3_assembler.c48 info->numwg = INVALID_REG; in ir3_parse_asm()
51 info->buf_addr_regs[i] = INVALID_REG; in ir3_parse_asm()
Dir3_spill.c505 if (dst->instr->opc == OPC_META_INPUT && dst->num != INVALID_REG) { in insert_dst()
645 struct ir3_register *mov_src = ir3_src_create(mov, INVALID_REG, src->flags); in materialize_pcopy_src()
676 ir3_src_create(spill, INVALID_REG, ctx->base_reg->flags)->def = ctx->base_reg; in spill()
680 struct ir3_register *src = ir3_src_create(spill, INVALID_REG, src_flags); in spill()
681 ir3_src_create(spill, INVALID_REG, IR3_REG_IMMED)->uim_val = elems; in spill()
787 struct ir3_register *src = ir3_src_create(split, INVALID_REG, def->flags); in split()
812 ir3_src_create(collect, INVALID_REG, parent_def->flags)->def = in extract()
835 ir3_src_create(reload, INVALID_REG, ctx->base_reg->flags)->def = ctx->base_reg; in reload()
837 ir3_src_create(reload, INVALID_REG, IR3_REG_IMMED); in reload()
839 ir3_src_create(reload, INVALID_REG, IR3_REG_IMMED)->uim_val = elems; in reload()
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Dinstr-a3xx.h422 #define INVALID_REG regid(63, 0) macro
423 #define VALIDREG(r) ((r) != INVALID_REG)
Dir3_ra.c1330 ir3_dst_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1340 ir3_src_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1520 if (instr->dsts[0]->num == INVALID_REG) in handle_precolored_input()
1533 if (instr->dsts[0]->num != INVALID_REG) in handle_input()
1549 if (instr->dsts[0]->num == INVALID_REG) { in assign_input()
1613 assert(src->num != INVALID_REG); in handle_chmask()
1778 ir3_dst_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
1788 ir3_src_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
2131 if (dst->num != INVALID_REG) { in calc_min_limit_pressure()
Dir3_context.c594 src->array.base = INVALID_REG; in ir3_create_array_load()
629 dst->array.base = INVALID_REG; in ir3_create_array_store()
659 dst->array.base = INVALID_REG; in ir3_create_array_store()
Dir3_print.c222 if (reg->num != INVALID_REG && !(reg->flags & IR3_REG_ARRAY)) in print_ssa_name()
270 if (reg->array.base != INVALID_REG) in print_reg_name()
Dir3_lower_subgroups.c67 mov, INVALID_REG, (dst->flags & IR3_REG_HALF) | IR3_REG_IMMED); in mov_immed()
Dir3_array_to_ssa.c126 src_reg = ir3_src_create(phi, INVALID_REG, flags | IR3_REG_SSA); in read_value_beginning()
Dir3.h1709 reg = ir3_src_create(instr, INVALID_REG, IR3_REG_SSA | flags); in __ssa_src()
1718 struct ir3_register *reg = ir3_dst_create(instr, INVALID_REG, IR3_REG_SSA); in __ssa_dst()
Dir3_shader.c210 info.numwg = INVALID_REG; in try_override_shader_variant()
Dir3_compiler_nir.c2833 ir3_src_create(continue_phi, INVALID_REG, phi->dsts[0]->flags); in read_phi_src()
2873 ir3_src_create(phi, INVALID_REG, phi->dsts[0]->flags); in resolve_phis()
4291 so->inputs[i].regid = INVALID_REG; in ir3_compile_shader_nir()
4293 so->outputs[i].regid = INVALID_REG; in ir3_compile_shader_nir()
/third_party/mesa3d/src/freedreno/computerator/
Da6xx.c250 if (ir3_kernel->info.numwg != INVALID_REG) { in cs_const_emit()
259 if (kernel->buf_addr_regs[i] != INVALID_REG) { in cs_const_emit()
Da4xx.c169 if (kernel->buf_addr_regs[i] != INVALID_REG) { in emit_const()
/third_party/mesa3d/src/freedreno/vulkan/
Dtu_pipeline.c768 if (k >= v->outputs_count || v->outputs[k].regid == INVALID_REG) in tu6_setup_streamout()