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Searched refs:Imm (Results 1 – 25 of 313) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
119 return Imm & 0x7; in getArithShiftValue()
123 static inline AArch64_AM::ShiftExtendType getExtendType(unsigned Imm) { in getExtendType() argument
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
120 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } in getSOImmValImm() argument
123 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } in getSOImmValRot() argument
129 inline unsigned getSOImmValRotate(unsigned Imm) { in getSOImmValRotate() argument
132 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate()
135 unsigned TZ = countTrailingZeros(Imm); in getSOImmValRotate()
142 if ((rotr32(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate()
147 if (Imm & 63U) { in getSOImmValRotate()
148 unsigned TZ2 = countTrailingZeros(Imm & ~63U); in getSOImmValRotate()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsAnalyzeImmediate.cpp32 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, in GetInstSeqLsADDiu() argument
34 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsADDiu()
35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
38 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, in GetInstSeqLsORi() argument
40 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsORi()
41 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); in GetInstSeqLsORi()
44 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, in GetInstSeqLsSLL() argument
46 unsigned Shamt = countTrailingZeros(Imm); in GetInstSeqLsSLL()
47 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL()
51 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize, in GetInstSeqLs() argument
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DMipsISelDAGToDAG.h98 virtual bool selectVSplat(SDNode *N, APInt &Imm,
101 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
103 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
105 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
107 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
109 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
111 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
113 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
115 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
117 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const;
[all …]
DMipsSEISelDAGToDAG.h96 bool selectVSplat(SDNode *N, APInt &Imm,
99 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
102 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
104 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
106 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
108 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
110 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
112 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
114 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
116 bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override;
[all …]
DMipsISelDAGToDAG.cpp154 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, in selectVSplat() argument
160 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { in selectVSplatUimm1()
165 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { in selectVSplatUimm2()
170 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { in selectVSplatUimm3()
175 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { in selectVSplatUimm4()
180 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { in selectVSplatUimm5()
185 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { in selectVSplatUimm6()
190 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { in selectVSplatUimm8()
195 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { in selectVSplatSimm5()
200 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const { in selectVSplatUimmPow2()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DAMDGPUInstPrinter.cpp53 int64_t Imm = MI->getOperand(OpNo).getImm(); in printU16ImmOperand() local
54 if (isInt<16>(Imm) || isUInt<16>(Imm)) in printU16ImmOperand()
55 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); in printU16ImmOperand()
114 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset() local
115 if (Imm != 0) { in printOffset()
124 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printFlatOffset() local
125 if (Imm != 0) { in printFlatOffset()
349 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm, in printImmediate16() argument
352 int16_t SImm = static_cast<int16_t>(Imm); in printImmediate16()
358 if (Imm == 0x3C00) in printImmediate16()
[all …]
DSIMCCodeEmitter.cpp98 static uint32_t getIntInlineImmEncoding(IntTy Imm) { in getIntInlineImmEncoding() argument
99 if (Imm >= 0 && Imm <= 64) in getIntInlineImmEncoding()
100 return 128 + Imm; in getIntInlineImmEncoding()
102 if (Imm >= -16 && Imm <= -1) in getIntInlineImmEncoding()
103 return 192 + std::abs(Imm); in getIntInlineImmEncoding()
219 int64_t Imm; in getLitEncoding() local
225 Imm = C->getValue(); in getLitEncoding()
233 Imm = MO.getImm(); in getLitEncoding()
243 return getLit32Encoding(static_cast<uint32_t>(Imm), STI); in getLitEncoding()
249 return getLit64Encoding(static_cast<uint64_t>(Imm), STI); in getLitEncoding()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp171 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { in decodeUImmOperand() argument
172 if (!isUInt<N>(Imm)) in decodeUImmOperand()
174 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
179 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { in decodeSImmOperand() argument
180 if (!isUInt<N>(Imm)) in decodeSImmOperand()
182 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
186 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU1ImmOperand() argument
188 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
191 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU2ImmOperand() argument
193 return decodeUImmOperand<2>(Inst, Imm); in decodeU2ImmOperand()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp246 ImmOp Imm; member
263 Imm = o.Imm; in RISCVOperand()
285 static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, in evaluateConstantImm()
289 return RE->evaluateAsConstant(Imm); in evaluateConstantImm()
294 Imm = CE->getValue(); in evaluateConstantImm()
304 int64_t Imm; in isBareSimmNLsb0() local
308 bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); in isBareSimmNLsb0()
311 IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm); in isBareSimmNLsb0()
313 IsValid = isShiftedInt<N - 1, 1>(Imm); in isBareSimmNLsb0()
320 int64_t Imm; in isBareSymbol() local
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ExpandImm.cpp23 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { in getChunk() argument
26 return (Imm >> (ChunkIdx * 16)) & 0xFFFF; in getChunk()
126 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) { in updateImm() argument
131 Imm &= ~(Mask << (Idx * 16)); in updateImm()
134 Imm |= Mask << (Idx * 16); in updateImm()
136 return Imm; in updateImm()
246 static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize, in expandMOVImmSimple() argument
260 Imm = ~Imm; in expandMOVImmSimple()
265 Imm &= (1LL << 32) - 1; in expandMOVImmSimple()
272 if (Imm != 0) { in expandMOVImmSimple()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp63 static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm, in DecodePCRel24BranchTarget() argument
66 int32_t Offset = SignExtend32<24>(Imm); in DecodePCRel24BranchTarget()
179 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, in decodeUImmOperand() argument
181 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeUImmOperand()
182 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
187 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, in decodeSImmOperand() argument
189 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeSImmOperand()
190 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
194 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, in decodeMemRIOperands() argument
199 uint64_t Base = Imm >> 16; in decodeMemRIOperands()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.h30 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
51 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm,
54 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm,
57 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm,
60 void DecodeVALIGNMask(unsigned NumElts, unsigned Imm,
66 void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
72 void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm,
78 void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm,
87 void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
115 void DecodeBLENDMask(unsigned NumElts, unsigned Imm,
[all …]
DX86ShuffleDecode.cpp23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodeINSERTPSMask() argument
31 unsigned ZMask = Imm & 15; in DecodeINSERTPSMask()
32 unsigned CountD = (Imm >> 4) & 3; in DecodeINSERTPSMask()
33 unsigned CountS = (Imm >> 6) & 3; in DecodeINSERTPSMask()
96 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, in DecodePSLLDQMask() argument
103 if (i >= Imm) M = i - Imm + l; in DecodePSLLDQMask()
108 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, in DecodePSRLDQMask() argument
114 unsigned Base = i + Imm; in DecodePSRLDQMask()
121 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, in DecodePALIGNRMask() argument
127 unsigned Base = i + Imm; in DecodePALIGNRMask()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/MCTargetDesc/
DNVPTXInstPrinter.cpp101 int64_t Imm = MO.getImm(); in printCvtMode() local
105 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) in printCvtMode()
109 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) in printCvtMode()
113 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { in printCvtMode()
151 int64_t Imm = MO.getImm(); in printCmpMode() local
155 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) in printCmpMode()
158 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { in printCmpMode()
225 int Imm = (int) MO.getImm(); in printLdStCode() local
227 if (Imm) in printLdStCode()
230 switch (Imm) { in printLdStCode()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVTargetTransformInfo.cpp18 int RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { in getIntImmCost() argument
23 if (Imm == 0) in getIntImmCost()
28 return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty), in getIntImmCost()
32 int RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, in getIntImmCostInst() argument
38 if (Imm == 0) in getIntImmCostInst()
74 if (Imm.getMinSignedBits() <= 64 && in getIntImmCostInst()
75 getTLI()->isLegalAddImmediate(Imm.getSExtValue())) { in getIntImmCostInst()
81 return getIntImmCost(Imm, Ty); in getIntImmCostInst()
89 const APInt &Imm, Type *Ty) { in getIntImmCostIntrin() argument
DRISCVInstrInfoC.td23 return isUInt<6>(Imm) && (Imm != 0);
24 return isUInt<5>(Imm) && (Imm != 0);
30 int64_t Imm;
31 if (!MCOp.evaluateAsConstantImm(Imm))
34 return isUInt<6>(Imm) && (Imm != 0);
35 return isUInt<5>(Imm) && (Imm != 0);
39 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
44 int64_t Imm;
45 if (MCOp.evaluateAsConstantImm(Imm))
46 return isInt<6>(Imm);
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Disassembler/
DRISCVDisassembler.cpp170 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, in decodeUImmOperand() argument
172 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeUImmOperand()
174 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
179 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, in decodeUImmNonZeroOperand() argument
182 if (Imm == 0) in decodeUImmNonZeroOperand()
184 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder); in decodeUImmNonZeroOperand()
188 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, in decodeSImmOperand() argument
190 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeSImmOperand()
193 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
198 static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, in decodeSImmNonZeroOperand() argument
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiTargetTransformInfo.h52 int getIntImmCost(const APInt &Imm, Type *Ty) { in getIntImmCost() argument
54 if (Imm == 0) in getIntImmCost()
56 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
58 if (isInt<21>(Imm.getZExtValue())) in getIntImmCost()
60 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
61 if ((Imm.getSExtValue() & 0xFFFF) == 0) in getIntImmCost()
69 int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) { in getIntImmCostInst() argument
70 return getIntImmCost(Imm, Ty); in getIntImmCostInst()
73 int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, in getIntImmCostIntrin() argument
75 return getIntImmCost(Imm, Ty); in getIntImmCostIntrin()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp90 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, in decodeSoppBrTarget() argument
96 APInt SignedOffset(18, Imm * 4, true); in decodeSoppBrTarget()
101 return addOperand(Inst, MCOperand::createImm(Imm)); in decodeSoppBrTarget()
112 unsigned Imm, \
116 return addOperand(Inst, DAsm->DecoderName(Imm)); \
150 unsigned Imm, in DECODE_OPERAND_REG()
154 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); in DECODE_OPERAND_REG()
158 unsigned Imm, in decodeOperand_VSrcV216() argument
162 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); in decodeOperand_VSrcV216()
166 unsigned Imm, in decodeOperand_VS_16() argument
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZTargetTransformInfo.cpp33 int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { in getIntImmCost() argument
45 if (Imm == 0) in getIntImmCost()
48 if (Imm.getBitWidth() <= 64) { in getIntImmCost()
50 if (isInt<32>(Imm.getSExtValue())) in getIntImmCost()
53 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
56 if ((Imm.getZExtValue() & 0xffffffff) == 0) in getIntImmCost()
66 const APInt &Imm, Type *Ty) { in getIntImmCostInst() argument
89 if (Idx == 0 && Imm.getBitWidth() <= 64) { in getIntImmCostInst()
94 if (isInt<16>(Imm.getSExtValue())) in getIntImmCostInst()
99 if (Idx == 1 && Imm.getBitWidth() <= 64) { in getIntImmCostInst()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86ATTInstPrinter.cpp85 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm(); in printVecCompareInstr() local
98 if (Imm >= 0 && Imm <= 7) { in printVecCompareInstr()
156 if (Imm >= 0 && Imm <= 31) { in printVecCompareInstr()
221 if (Imm >= 0 && Imm <= 7) { in printVecCompareInstr()
298 if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) { in printVecCompareInstr()
360 int64_t Imm = Op.getImm(); in printOperand() local
361 O << markup("<imm:") << '$' << formatImm(Imm) << markup(">"); in printOperand()
369 if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) { in printOperand()
371 if (Imm == (int16_t)(Imm)) in printOperand()
372 *CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm); in printOperand()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp117 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
120 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
123 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
125 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
127 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
129 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
177 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
179 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
182 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
184 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DDataMov.cpp177 #define TestMovzx8bitWithRegDest(Src, Dst, Imm) \ in TEST_F() argument
179 static_assert(((Imm)&0xFF) == (Imm), #Imm " is not an 8bit immediate"); \ in TEST_F()
180 __ mov(IceType_i8, GPRRegister::Encoded_Reg_##Src, Immediate(Imm)); \ in TEST_F()
185 ASSERT_EQ(Imm, test.Dst()) << "(" #Src ", " #Dst ", " #Imm ")"; \ in TEST_F()
189 #define TestMovzx16bitWithRegDest(Src, Dst, Imm) \ in TEST_F() argument
191 static_assert(((Imm)&0xFFFF) == (Imm), #Imm " is not a 16bit immediate"); \ in TEST_F()
192 __ mov(IceType_i16, GPRRegister::Encoded_Reg_##Src, Immediate(Imm)); \ in TEST_F()
197 ASSERT_EQ(Imm, test.Dst()) << "(" #Src ", " #Dst ", " #Imm ")"; \ in TEST_F()
201 #define TestMovzx8bitWithAddrSrc(Dst, Imm) \ in TEST_F() argument
203 static_assert(((Imm)&0xFF) == (Imm), #Imm " is not an 8bit immediate"); \ in TEST_F()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/MCTargetDesc/
DBPFInstPrinter.cpp76 auto Imm = OffsetOp.getImm(); in printMemOperand() local
77 if (Imm >= 0) in printMemOperand()
78 O << " + " << formatImm(Imm); in printMemOperand()
80 O << " - " << formatImm(-Imm); in printMemOperand()
101 int16_t Imm = Op.getImm(); in printBrTargetOperand() local
102 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm); in printBrTargetOperand()

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