| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 45 uint64_t &Size, uint16_t &Insn) { in readInstruction16() argument
52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
57 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
64 Insn = in readInstruction32()
92 unsigned Insn,
97 unsigned Insn,
102 unsigned Insn,
107 unsigned Insn,
112 unsigned Insn,
117 unsigned Insn,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 246 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
248 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
251 unsigned Insn,
254 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
256 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
258 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
260 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
264 unsigned Insn,
267 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
269 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 54 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
57 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
60 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
63 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
70 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
76 uint32_t &Insn) { in readInstruction32() argument
84 Insn = in readInstruction32()
90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
101 AluOp = (Insn >> 8) & 0x7; in PostOperandDecodeAdjust()
105 AluOp |= 0x20 | (((Insn >> 3) & 0xf) << 1); in PostOperandDecodeAdjust()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/Disassembler/ |
| D | ARCDisassembler.cpp | 51 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
54 Insn = in readInstruction32()
60 uint64_t &Size, uint64_t &Insn) { in readInstruction64() argument
62 Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) | in readInstruction64()
70 uint64_t &Size, uint64_t &Insn) { in readInstruction48() argument
72 Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | in readInstruction48()
79 uint64_t &Size, uint32_t &Insn) { in readInstruction16() argument
81 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
145 static unsigned decodeCField(unsigned Insn) { in decodeCField() argument
146 return fieldFromInstruction(Insn, 6, 6); in decodeCField()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 113 unsigned Insn,
147 unsigned Insn,
217 unsigned Insn,
267 unsigned Insn,
274 unsigned Insn,
279 unsigned Insn,
284 unsigned Insn,
289 unsigned Insn,
293 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
297 unsigned Insn,
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | InstructionPrecedenceTracking.cpp | 59 const Instruction *Insn) { in isPreceededBySpecialInstruction() argument
61 getFirstSpecialInstruction(Insn->getParent()); in isPreceededBySpecialInstruction()
62 return MaybeFirstSpecial && OI.dominates(MaybeFirstSpecial, Insn); in isPreceededBySpecialInstruction()
84 for (const Instruction &Insn : *BB) in validate()
85 if (isSpecialInstruction(&Insn)) { in validate()
86 assert(It->second == &Insn && in validate()
127 const Instruction *Insn) const { in isSpecialInstruction()
140 if (isGuaranteedToTransferExecutionToSuccessor(Insn)) in isSpecialInstruction()
142 if (isa<LoadInst>(Insn)) { in isSpecialInstruction()
143 assert(cast<LoadInst>(Insn)->isVolatile() && in isSpecialInstruction()
[all …]
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| D | GuardUtils.cpp | 35 for (auto &Insn : *DeoptBB) { in isGuardAsWidenableBranch()
36 if (match(&Insn, m_Intrinsic<Intrinsic::experimental_deoptimize>())) in isGuardAsWidenableBranch()
38 if (Insn.mayHaveSideEffects()) in isGuardAsWidenableBranch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandImm.cpp | 45 SmallVectorImpl<ImmInsnModel> &Insn) { in tryToreplicateChunks() argument
69 Insn.push_back({ AArch64::ORRXri, 0, Encoding }); in tryToreplicateChunks()
82 Insn.push_back({ AArch64::MOVKXi, Imm16, in tryToreplicateChunks()
97 Insn.push_back({ AArch64::MOVKXi, Imm16, in tryToreplicateChunks()
153 SmallVectorImpl<ImmInsnModel> &Insn) { in trySequenceOfOnes() argument
225 Insn.push_back({ AArch64::ORRXri, 0, Encoding }); in trySequenceOfOnes()
228 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, FirstMovkIdx), in trySequenceOfOnes()
237 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx), in trySequenceOfOnes()
248 SmallVectorImpl<ImmInsnModel> &Insn) { in expandMOVImmSimple() argument
280 Insn.push_back({ FirstOpc, Imm16, in expandMOVImmSimple()
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| D | AArch64ExpandImm.h | 29 SmallVectorImpl<ImmInsnModel> &Insn);
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| D | AArch64ExpandPseudoInsts.cpp | 124 SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn; in expandMOVImm() local
125 AArch64_IMM::expandMOVImm(Imm, BitSize, Insn); in expandMOVImm()
126 assert(Insn.size() != 0); in expandMOVImm()
129 for (auto I = Insn.begin(), E = Insn.end(); I != E; ++I) { in expandMOVImm()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Disassembler/ |
| D | RISCVDisassembler.cpp | 240 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
243 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
246 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
250 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
253 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
259 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, in decodeRVCInstrSImm() argument
262 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrSImm()
269 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, in decodeRVCInstrRdSImm() argument
274 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdSImm()
281 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, in decodeRVCInstrRdRs1UImm() argument
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/ |
| D | MSP430Disassembler.cpp | 181 static AddrMode DecodeSrcAddrModeI(unsigned Insn) { in DecodeSrcAddrModeI() argument
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI()
183 unsigned As = fieldFromInstruction(Insn, 4, 2); in DecodeSrcAddrModeI()
187 static AddrMode DecodeSrcAddrModeII(unsigned Insn) { in DecodeSrcAddrModeII() argument
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII()
189 unsigned As = fieldFromInstruction(Insn, 4, 2); in DecodeSrcAddrModeII()
193 static AddrMode DecodeDstAddrMode(unsigned Insn) { in DecodeDstAddrMode() argument
194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode()
195 unsigned Ad = fieldFromInstruction(Insn, 7, 1); in DecodeDstAddrMode()
233 uint64_t Insn = support::endian::read16le(Bytes.data()); in getInstructionI() local
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/ |
| D | InstructionPrecedenceTracking.h | 65 bool isPreceededBySpecialInstruction(const Instruction *Insn);
72 virtual bool isSpecialInstruction(const Instruction *Insn) const = 0;
115 bool isDominatedByICFIFromSameBlock(const Instruction *Insn) { in isDominatedByICFIFromSameBlock() argument
116 return isPreceededBySpecialInstruction(Insn); in isDominatedByICFIFromSameBlock()
119 virtual bool isSpecialInstruction(const Instruction *Insn) const;
140 bool isDominatedByMemoryWriteFromSameBlock(const Instruction *Insn) { in isDominatedByMemoryWriteFromSameBlock() argument
141 return isPreceededBySpecialInstruction(Insn); in isDominatedByMemoryWriteFromSameBlock()
144 virtual bool isSpecialInstruction(const Instruction *Insn) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/Disassembler/ |
| D | AVRDisassembler.cpp | 78 uint64_t &Size, uint32_t &Insn) { in readInstruction16() argument
85 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
91 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
99 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24); in readInstruction32()
117 uint32_t Insn; in getInstruction() local
123 Result = readInstruction16(Bytes, Address, Size, Insn); in getInstruction()
129 Insn, Address, this, STI); in getInstruction()
137 Result = readInstruction32(Bytes, Address, Size, Insn); in getInstruction()
141 Result = decodeInstruction(getDecoderTable(Size), Instr, Insn, in getInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/Disassembler/ |
| D | BPFDisassembler.cpp | 126 static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn, in decodeMemoryOpValue() argument
128 unsigned Register = (Insn >> 16) & 0xf; in decodeMemoryOpValue()
130 unsigned Offset = (Insn & 0xffff); in decodeMemoryOpValue()
138 uint64_t &Size, uint64_t &Insn, in readInstruction64() argument
156 Insn = Make_64(Hi, Lo); in readInstruction64()
166 uint64_t Insn, Hi; in getInstruction() local
169 Result = readInstruction64(Bytes, Address, Size, Insn, IsLittleEndian); in getInstruction()
172 uint8_t InstClass = getInstClass(Insn); in getInstruction()
173 uint8_t InstMode = getInstMode(Insn); in getInstruction()
175 getInstSize(Insn) != BPF_DW && in getInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/ |
| D | RuntimeDyldELFMips.cpp | 215 uint32_t Insn = readBytesUnaligned(TargetPtr, 4); in applyMIPSRelocation() local
233 Insn = (Insn & 0xffff0000) | (Value & 0x0000ffff); in applyMIPSRelocation()
234 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
237 Insn = (Insn & 0xfffc0000) | (Value & 0x0003ffff); in applyMIPSRelocation()
238 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
241 Insn = (Insn & 0xfff80000) | (Value & 0x0007ffff); in applyMIPSRelocation()
242 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
245 Insn = (Insn & 0xffe00000) | (Value & 0x001fffff); in applyMIPSRelocation()
246 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
250 Insn = (Insn & 0xfc000000) | (Value & 0x03ffffff); in applyMIPSRelocation()
[all …]
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| D | RuntimeDyldMachOARM.h | 272 uint32_t Insn = readBytesUnaligned(LocalAddress, 4); in resolveRelocation() local
275 Insn = (Insn & 0x8f00fbf0) | ((Value & 0xf000) >> 12) | in resolveRelocation()
279 Insn = (Insn & 0xfff0f000) | ((Value & 0xf000) << 4) | (Value & 0x0fff); in resolveRelocation()
280 writeBytesUnaligned(Insn, LocalAddress, 4); in resolveRelocation()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 1705 InternalInstruction Insn; in getInstruction() local
1706 memset(&Insn, 0, sizeof(InternalInstruction)); in getInstruction()
1707 Insn.bytes = Bytes; in getInstruction()
1708 Insn.startLocation = Address; in getInstruction()
1709 Insn.readerCursor = Address; in getInstruction()
1710 Insn.mode = fMode; in getInstruction()
1712 if (Bytes.empty() || readPrefixes(&Insn) || readOpcode(&Insn) || in getInstruction()
1713 getInstructionID(&Insn, MII.get()) || Insn.instructionID == 0 || in getInstruction()
1714 readOperands(&Insn)) { in getInstruction()
1715 Size = Insn.readerCursor - Address; in getInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCTargetDesc.cpp | 336 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte); in findPltEntries() local
339 if (Insn == 0xd503245f) { in findPltEntries()
341 Insn = support::endian::read32le(PltContents.data() + Byte + Off); in findPltEntries()
344 if ((Insn & 0x9f000000) != 0x90000000) in findPltEntries()
348 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14); in findPltEntries()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | GVNHoist.cpp | 398 Instruction *Insn = MU->getMemoryInst(); in hasMemoryUse() local
401 if (BB == OldBB && firstInBB(OldPt, Insn)) in hasMemoryUse()
407 if (firstInBB(Insn, NewPt)) in hasMemoryUse()
601 Instruction *Insn = CHI.I; in checkSafety() local
602 if (!Insn) // No instruction was inserted in this CHI. in checkSafety()
605 if (safeToHoistScalar(BB, Insn->getParent(), NumBBsOnAllPaths)) in checkSafety()
608 MemoryUseOrDef *UD = MSSA->getMemoryAccess(Insn); in checkSafety()
609 if (safeToHoistLdSt(BB->getTerminator(), Insn, UD, K, NumBBsOnAllPaths)) in checkSafety()
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| D | GuardWidening.cpp | 284 static bool isSupportedGuardInstruction(const Instruction *Insn) { in isSupportedGuardInstruction() argument
285 if (isGuard(Insn)) in isSupportedGuardInstruction()
287 if (WidenBranchGuards && isGuardAsWidenableBranch(Insn)) in isSupportedGuardInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 314 uint64_t &Size, uint32_t &Insn, in readInstruction32() argument
322 Insn = IsLittleEndian in readInstruction32()
335 uint32_t Insn; in getInstruction() local
338 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian); in getInstruction()
346 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI); in getInstruction()
350 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI); in getInstruction()
356 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); in getInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrFormatsV5.td | 75 let TSFlags{17} = isExtendable; // Insn may be extended.
77 let TSFlags{18} = isExtended; // Insn must be extended.
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| D | HexagonInstrFormats.td | 111 let TSFlags{23} = isExtendable; // Insn may be extended.
113 let TSFlags{24} = isExtended; // Insn must be extended.
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 174 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
264 uint32_t Insn = in getInstruction() local
268 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); in getInstruction()
840 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, in DecodeFMOVLaneInstruction() argument
845 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction()
846 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction()
847 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); in DecodeFMOVLaneInstruction()
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