Searched refs:LDP (Results 1 – 18 of 18) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | LoopDataPrefetch.cpp | 166 LoopDataPrefetch LDP(AC, LI, SE, TTI, ORE); in run() local
167 bool Changed = LDP.run(); in run()
192 LoopDataPrefetch LDP(AC, LI, SE, TTI, ORE); in runOnFunction() local
193 return LDP.run(); in runOnFunction()
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| /third_party/node/deps/npm/node_modules/term-size/ |
| D | readme.md | 5 …am_columns) doesn't exist when run [non-interactively](http://www.tldp.org/LDP/abs/html/intandnoni…
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64Schedule.td | 61 // LDP,LDPSW,LDNP,LDXP,LDAXP
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| D | AArch64FalkorHWPFFix.cpp | 133 FalkorMarkStridedAccesses LDP(LI, SE); in runOnFunction() local
134 return LDP.run(); in runOnFunction()
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| D | AArch64SchedFalkorDetails.td | 1106 (instregex "LDP(D|S)i$")>;
1108 (instregex "LDP(D|S)(pre|post)$")>;
1170 (instregex "^LDP(W|X)i$")>;
1172 (instregex "^LDP(W|X)(post|pre)$")>;
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| D | AArch64SchedExynosM4.td | 612 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
693 WriteAdr], (instregex "^LDP[SD]post")>;
699 WriteAdr], (instregex "^LDP[SD]pre")>;
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| D | AArch64SchedExynosM3.td | 515 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
578 WriteAdr], (instregex "^LDP[DS](post|pre)")>;
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| D | AArch64ISelLowering.h | 278 LDP, enumerator
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| D | AArch64SchedExynosM5.td | 669 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
749 WriteAdr], (instregex "^LDP[SD](post|pre)")>;
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| D | AArch64SchedCyclone.td | 267 // LDP high register write is fused with the load, but a nop micro-op remains.
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| D | AArch64SchedKryoDetails.td | 1420 (instregex "LDP(D|S)(post|pre)")>;
1432 (instregex "LDP(W|X)(post|pre)")>;
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| D | AArch64SchedThunderX2T99.td | 610 // LDP only breaks into *one* LS micro-op. Thus
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| D | AArch64ISelLowering.cpp | 1407 case AArch64ISD::LDP: return "AArch64ISD::LDP"; in getTargetNodeName()
12977 AArch64ISD::LDP, SDLoc(N), in ReplaceNodeResults()
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| D | AArch64InstrInfo.td | 552 def AArch64ldp : SDNode<"AArch64ISD::LDP", SDT_AArch64ldp, [SDNPHasChain, SDNPMayLoad, SDNPMemOpera…
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_64.c | 99 #define LDP 0xa9400000 macro
1076 FAIL_IF(push_inst(compiler, LDP | RT(TMP_FP) | RT2(TMP_LR) | RN(SLJIT_SP))); in sljit_emit_return()
1089 FAIL_IF(push_inst(compiler, LDP | RT(TMP_FP) | RT2(TMP_LR) | RN(SLJIT_SP))); in sljit_emit_return()
1100 FAIL_IF(push_inst(compiler, LDP | RT(prev) | RT2(i) | RN(SLJIT_SP) | offs)); in sljit_emit_return()
1110 FAIL_IF(push_inst(compiler, LDP | RT(prev) | RT2(i) | RN(SLJIT_SP) | offs)); in sljit_emit_return()
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| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3.h | 2151 INSTR3(LDP)
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.0.0.rst | 786 - ir3: Fix STP/LDP assembly
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| /third_party/eudev/hwdb/ |
| D | 20-usb-vendor-model.hwdb | 44112 ID_MODEL_FROM_DATABASE=LG LDP-7024D(LD)USB
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