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Searched refs:MAX_SAMPLES_LOG2 (Results 1 – 8 of 8) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
Dradv_constants.h45 #define MAX_SAMPLES_LOG2 4 macro
Dradv_private.h429 } clear[MAX_SAMPLES_LOG2];
483 } blit2d[MAX_SAMPLES_LOG2];
509 VkPipeline pipeline[MAX_SAMPLES_LOG2];
520 VkPipeline pipeline[MAX_SAMPLES_LOG2];
542 } rc[MAX_SAMPLES_LOG2];
549 } depth[MAX_SAMPLES_LOG2];
555 } stencil[MAX_SAMPLES_LOG2];
565 } rc[MAX_SAMPLES_LOG2];
573 } depth[MAX_SAMPLES_LOG2];
580 } stencil[MAX_SAMPLES_LOG2];
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Dradv_meta_fmask_expand.c175 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) { in radv_device_finish_meta_fmask_expand_state()
258 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; i++) { in radv_device_init_meta_fmask_expand_state()
Dradv_meta_bufimage.c697 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; i++) { in radv_device_init_meta_itoi_state()
743 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) { in radv_device_finish_meta_itoi_state()
1016 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; i++) { in radv_device_init_meta_cleari_state()
1063 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) { in radv_device_finish_meta_cleari_state()
Dradv_meta_resolve_cs.c384 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) { in radv_device_init_meta_resolve_compute_state()
455 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) { in radv_device_finish_meta_resolve_compute_state()
Dradv_meta_resolve_fs.c660 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) { in radv_device_init_meta_resolve_fragment_state()
713 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) { in radv_device_finish_meta_resolve_fragment_state()
Dradv_meta_blit2d.c648 for (unsigned log2_samples = 0; log2_samples < MAX_SAMPLES_LOG2; ++log2_samples) { in radv_device_finish_meta_blit2d_state()
1315 for (unsigned log2_samples = 0; log2_samples < MAX_SAMPLES_LOG2; log2_samples++) { in radv_device_init_meta_blit2d_state()
/third_party/mesa3d/src/panfrost/vulkan/
Dpanvk_private.h99 #define MAX_SAMPLES_LOG2 4 macro