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Searched refs:MUBUF (Results 1 – 23 of 23) sorted by relevance

/third_party/mesa3d/src/amd/compiler/
Daco_opcodes.py62 MUBUF = 10 variable in Format
106 elif self == Format.MUBUF:
1284 MUBUF = { variable
1366 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in MUBUF:
1367 opcode(name, gfx7, gfx9, gfx10, Format.MUBUF, InstrClass.VMem, is_atomic = "atomic" in name)
Daco_opt_value_numbering.cpp103 case Format::MUBUF: return hash_murmur_32<MUBUF_instruction>(instr); in operator ()()
251 case Format::MUBUF: { in operator ()()
339 case Format::MUBUF: in can_eliminate()
DREADME-ISA.md185 ## SGPR offset on MUBUF prevents addr clamping on SI/CI
Daco_ir.cpp173 case Format::MUBUF: return instr->mubuf().sync; in get_sync_info()
Daco_ir.h83 MUBUF = 10, enumerator
1130 constexpr bool isMUBUF() const noexcept { return format == Format::MUBUF; } in isMUBUF()
Daco_insert_waitcnt.cpp673 case Format::MUBUF: in gen()
Daco_print_ir.cpp364 case Format::MUBUF: { in print_instr_format_specific()
Daco_assembler.cpp380 case Format::MUBUF: { in emit_instruction()
Daco_validate.cpp532 case Format::MUBUF: { in validate_ir()
Daco_instruction_selection.cpp4067 aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)}; in mubuf_load_callback()
4143 create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)}; in global_load_callback()
6174 create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3 + is_sparse, 1)}; in visit_image_load()
6251 create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)}; in visit_image_store()
6382 is_64bit ? buf_op64 : buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)}; in visit_image_atomic()
6578 create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)}; in visit_store_ssbo()
6666 create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)}; in visit_atomic_ssbo()
6814 create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)}; in visit_store_global()
6983 create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)}; in visit_global_atomic()
8020 aco_opcode::buffer_load_dwordx2, Format::MUBUF, 3, 1)}; in visit_intrinsic()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td38 field bit MUBUF = 0;
150 let TSFlags{16} = MUBUF;
DSIDefines.h45 MUBUF = 1 << 16, enumerator
DSIInstrInfo.h446 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
450 return get(Opcode).TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
DBUFInstructions.td293 // MUBUF classes
320 let MUBUF = 1;
776 // MUBUF Instructions
1152 // MUBUF Patterns
1851 // MUBUF - GFX10.
1930 // MUBUF - GFX6, GFX7, GFX10.
DAMDGPU.td587 // to missing ADDR64 variants of MUBUF instructions.
588 // FIXME: moveToVALU should be able to handle converting addr64 MUBUF
DSMInstructions.td791 // Global and constant loads can be selected to either MUBUF or SMRD
/third_party/mesa3d/docs/relnotes/
D20.3.5.rst244 - radv,aco: don't use MUBUF for multi-channel loads on GFX8 with robustness2
D20.0.0.rst758 - aco: use soffset for MUBUF instructions on SI/CI
2879 - aco: value-number MUBUF instructions
2880 - aco: use MUBUF in some situations instead of splitting vertex fetches
3182 - aco: fix emitting slc for MUBUF instructions on GFX6-GFX7
3188 - aco: add new addr64 bit to MUBUF instructions on GFX6-GFX7
3238 - aco: fix VS input loads with MUBUF on GFX6
3243 - aco: fix MUBUF VS input loads when expanding vec3 to vec4 on GFX6
D20.1.0.rst1225 - aco: use MUBUF to load subdword SSBO
3816 - aco: fix MUBUF VS input loads when expanding vec3 to vec4 on GFX6
D21.1.0.rst4711 - radv,aco: don't use MUBUF for multi-channel loads on GFX8 with robustness2
4789 - aco: fix NSA MIMG followed by MUBUF/MTBUF
D21.0.0.rst2810 - radv,aco: don't use MUBUF for multi-channel loads on GFX8 with robustness2
D19.3.0.rst3285 - aco: Support GFX10 MUBUF in aco_assembler.
D21.2.0.rst4418 - Revert "radv,aco: don't use MUBUF for multi-channel loads on GFX8 with robustness2"