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Searched refs:OUT_REG (Results 1 – 10 of 10) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_rasterizer.c54 OUT_REG(ring, A6XX_GRAS_CL_CNTL(.znear_clip_disable = !cso->depth_clip_near, in __fd6_setup_rasterizer_stateobj()
61 OUT_REG(ring, in __fd6_setup_rasterizer_stateobj()
69 OUT_REG(ring, in __fd6_setup_rasterizer_stateobj()
73 OUT_REG(ring, A6XX_GRAS_SU_POLY_OFFSET_SCALE(cso->offset_scale), in __fd6_setup_rasterizer_stateobj()
77 OUT_REG(ring, in __fd6_setup_rasterizer_stateobj()
94 OUT_REG(ring, A6XX_VPC_POLYGON_MODE(mode)); in __fd6_setup_rasterizer_stateobj()
95 OUT_REG(ring, A6XX_PC_POLYGON_MODE(mode)); in __fd6_setup_rasterizer_stateobj()
98 OUT_REG(ring, A6XX_RB_UNKNOWN_8A00()); in __fd6_setup_rasterizer_stateobj()
99 OUT_REG(ring, A6XX_RB_UNKNOWN_8A10()); in __fd6_setup_rasterizer_stateobj()
100 OUT_REG(ring, A6XX_RB_UNKNOWN_8A20()); in __fd6_setup_rasterizer_stateobj()
[all …]
Dfd6_blend.c91 OUT_REG(ring, in __fd6_setup_blend_variant()
100 OUT_REG(ring, A6XX_RB_MRT_CONTROL(i, .rop_code = rop, in __fd6_setup_blend_variant()
115 OUT_REG( in __fd6_setup_blend_variant()
128 OUT_REG(ring, A6XX_SP_BLEND_CNTL(.enable_blend = mrt_blend, in __fd6_setup_blend_variant()
134 OUT_REG(ring, in __fd6_setup_blend_variant()
Dfd6_gmem.c122 OUT_REG( in emit_mrt()
131 OUT_REG(ring, A6XX_SP_FS_MRT_REG(i, .color_format = format, in emit_mrt()
139 OUT_REG(ring, A6XX_RB_SRGB_CNTL(.dword = srgb_cntl)); in emit_mrt()
140 OUT_REG(ring, A6XX_SP_SRGB_CNTL(.dword = srgb_cntl)); in emit_mrt()
142 OUT_REG(ring, A6XX_GRAS_MAX_LAYER_INDEX(max_layer_index)); in emit_mrt()
158 OUT_REG( in emit_zs()
166 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt)); in emit_zs()
173 OUT_REG(ring, A6XX_GRAS_LRZ_BUFFER_BASE(.bo = rsc->lrz), in emit_zs()
198 OUT_REG(ring, A6XX_RB_STENCIL_INFO(.separate_stencil = true), in emit_zs()
206 OUT_REG(ring, A6XX_RB_STENCIL_INFO(0)); in emit_zs()
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Dfd6_emit.c703 OUT_REG(ring, in build_lrz()
707 OUT_REG(ring, A6XX_RB_LRZ_CNTL(.enable = lrz.enable, )); in build_lrz()
709 OUT_REG(ring, A6XX_RB_DEPTH_PLANE_CNTL(.z_mode = lrz.z_mode, )); in build_lrz()
711 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_PLANE_CNTL(.z_mode = lrz.z_mode, )); in build_lrz()
725 OUT_REG( in build_scissor()
793 OUT_REG(ring, A6XX_SP_FS_RENDER_COMPONENTS(.dword = mrt_components)); in build_prog_fb_rast()
794 OUT_REG(ring, A6XX_RB_RENDER_COMPONENTS(.dword = mrt_components)); in build_prog_fb_rast()
807 OUT_REG(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]), in build_blend_color()
961 OUT_REG(ring, A6XX_GRAS_CL_VPORT_XOFFSET(0, ctx->viewport.translate[0]), in fd6_emit_non_ring()
968 OUT_REG( in fd6_emit_non_ring()
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Dfd6_draw.c390 OUT_REG(ring, A6XX_RB_CCU_CNTL(.color_offset = screen->ccu_offset_bypass)); in fd6_clear_lrz()
392 OUT_REG(ring, in fd6_clear_lrz()
455 OUT_REG(ring, A6XX_GRAS_2D_SRC_TL_X(0), A6XX_GRAS_2D_SRC_BR_X(0), in fd6_clear_lrz()
Dfd6_pack.h72 #define OUT_REG(ring, ...) \ macro
Dfd6_compute.c48 OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true, in cs_program_emit()
Dfd6_program.c280 OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true, in setup_config_stateobj()
1033 OUT_REG(ring, A6XX_PC_PRIMID_PASSTHRU(primid_passthru)); in setup_stateobj()
/third_party/mesa3d/docs/relnotes/
D20.0.0.rst1100 - freedreno: Fix OUT_REG() on address regs without a .bo supplied.
2031 - freedreno/a6xx: Convert emit_mrt() to OUT_REG()
2032 - freedreno/a6xx: Convert emit_zs() to OUT_REG()
2033 - freedreno/a6xx: Convert VSC pipe setup to OUT_REG()
2034 - freedreno/a6xx: Convert gmem blits to OUT_REG()
2035 - freedreno/a6xx: Convert some tile setup to OUT_REG()
2967 - freedreno/a6xx: fix OUT_REG() vs growable cmdstream
D20.2.0.rst3990 - freedreno/a6xx: more OUT_REG()