Searched refs:Op5 (Results 1 – 7 of 7) sorted by relevance
| /third_party/grpc/include/grpcpp/impl/codegen/ |
| D | call_op_set.h | 851 class Op5 = CallNoOp<5>, class Op6 = CallNoOp<6>>
860 template <class Op1, class Op2, class Op3, class Op4, class Op5, class Op6>
866 public Op5,
920 this->Op5::FinishOp(status); in FinalizeResult()
950 this->Op5::SetHijackingState(&interceptor_methods_); in SetHijackingState()
963 this->Op5::AddOp(ops, &nops); in ContinueFillOpsAfterInterception()
1000 this->Op5::SetInterceptionHookPoint(&interceptor_methods_); in RunInterceptors()
1019 this->Op5::SetFinishInterceptionHookPoint(&interceptor_methods_); in RunInterceptorsPostRecv()
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| D | completion_queue_impl.h | 89 template <class Op1, class Op2, class Op3, class Op4, class Op5, class Op6>
294 template <class Op1, class Op2, class Op3, class Op4, class Op5, class Op6>
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| D | completion_queue.h | 92 template <class Op1, class Op2, class Op3, class Op4, class Op5, class Op6>
295 template <class Op1, class Op2, class Op3, class Op4, class Op5, class Op6>
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 647 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
652 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
659 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL6RInstruction()
681 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
686 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
694 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL5RInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6433 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); in tryConvertingToTwoOperandForm() local
6438 (Op5.isReg() && Op5.getReg() == ARM::PC); in tryConvertingToTwoOperandForm()
6441 (Op5.isReg() && Op5.getReg() == ARM::SP)) && in tryConvertingToTwoOperandForm()
6443 Op5.isImm() && !Op5.isImm0_508s4()); in tryConvertingToTwoOperandForm()
6464 const ARMOperand *LastOp = &Op5; in tryConvertingToTwoOperandForm()
6466 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && in tryConvertingToTwoOperandForm()
6492 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 1222 SDValue Op3, SDValue Op4, SDValue Op5);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 7688 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
7689 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
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