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Searched refs:PADDING_SIZE (Results 1 – 8 of 8) sorted by relevance

/third_party/mindspore/mindspore/ccsrc/backend/kernel_compiler/gpu/cuda_impl/
Dmirror_pad_impl.cuh24 #define PADDING_SIZE 2 macro
27 #define BATCH 0 * PADDING_SIZE
28 #define CHANNEL 1 * PADDING_SIZE
29 #define HEIGHT 2 * PADDING_SIZE
30 #define WIDTH 3 * PADDING_SIZE
Dmirror_pad_impl.cu33 extracted_paddings[(paddings_offset + i) * PADDING_SIZE] = paddings_arg[i * PADDING_SIZE]; in extract_paddings()
34 … extracted_paddings[(paddings_offset + i) * PADDING_SIZE + 1] = paddings_arg[i * PADDING_SIZE + 1]; in extract_paddings()
44 int64_t paddings[MAX_PADDINGS * PADDING_SIZE]; // local and fixed size to keep in registers in MirrorPad()
45 for (int i = 0; i < MAX_PADDINGS * PADDING_SIZE; i++) { in MirrorPad()
119 int64_t paddings[MAX_PADDINGS * PADDING_SIZE]; // local and fixed size to keep in registers in MirrorPadGradBatchChannel()
120 for (int i = 0; i < MAX_PADDINGS * PADDING_SIZE; i++) { in MirrorPadGradBatchChannel()
176 int64_t paddings[MAX_PADDINGS * PADDING_SIZE]; // local and fixed size to keep in registers in MirrorPadGrad_Width_Height()
177 for (int i = 0; i < MAX_PADDINGS * PADDING_SIZE; i++) { in MirrorPadGrad_Width_Height()
/third_party/mindspore/mindspore/ccsrc/backend/kernel_compiler/cpu/
Dmirror_pad_cpu_kernel.cc25 constexpr int PADDING_SIZE = 2; variable
28 constexpr int BATCH = 0 * PADDING_SIZE;
29 constexpr int CHANNEL = 1 * PADDING_SIZE;
30 constexpr int HEIGHT = 2 * PADDING_SIZE;
31 constexpr int WIDTH = 3 * PADDING_SIZE;
97 extracted_paddings[(paddings_offset + i) * PADDING_SIZE] = paddings_arg[i * PADDING_SIZE]; in extract_paddings()
98 … extracted_paddings[(paddings_offset + i) * PADDING_SIZE + 1] = paddings_arg[i * PADDING_SIZE + 1]; in extract_paddings()
139 int64_t paddings[MAX_PADDINGS * PADDING_SIZE]; // local and fixed size to keep in registers in LaunchKernel()
140 for (int i = 0; i < MAX_PADDINGS * PADDING_SIZE; i++) { in LaunchKernel()
Dmirror_pad_grad_cpu_kernel.cc25 constexpr int PADDING_SIZE = 2; variable
29 constexpr int CHANNEL = 1 * PADDING_SIZE;
30 constexpr int HEIGHT = 2 * PADDING_SIZE;
31 constexpr int WIDTH = 3 * PADDING_SIZE;
42 extracted_paddings[(paddings_offset + i) * PADDING_SIZE] = paddings_arg[i * PADDING_SIZE]; in extract_paddings()
43 … extracted_paddings[(paddings_offset + i) * PADDING_SIZE + 1] = paddings_arg[i * PADDING_SIZE + 1]; in extract_paddings()
165 int64_t paddings[MAX_PADDINGS * PADDING_SIZE]; // local and fixed size to keep in registers in MirrorPadGrad_Width_Height()
166 for (int i = 0; i < MAX_PADDINGS * PADDING_SIZE; i++) { in MirrorPadGrad_Width_Height()
230 int64_t paddings[MAX_PADDINGS * PADDING_SIZE]; // local and fixed size to keep in registers in MirrorPadGradBatchChannel()
231 for (int i = 0; i < MAX_PADDINGS * PADDING_SIZE; i++) { in MirrorPadGradBatchChannel()
/third_party/mesa3d/src/intel/tools/
Dintel_sanitize_gpu.c61 #define PADDING_SIZE 4096 macro
169 .size = PADDING_SIZE, in padding_is_good()
192 intel_invalidate_range(mapped, PADDING_SIZE); in padding_is_good()
195 for (uint32_t i = 0; i < PADDING_SIZE; ++i) { in padding_is_good()
197 munmap(mapped, PADDING_SIZE); in padding_is_good()
202 munmap(mapped, PADDING_SIZE); in padding_is_good()
212 create->size = align64(original_size, 4096) + PADDING_SIZE; in create_with_padding()
223 .size = PADDING_SIZE, in create_with_padding()
235 PADDING_SIZE); in create_with_padding()
236 munmap(noise_values, PADDING_SIZE); in create_with_padding()
/third_party/ltp/testcases/kernel/syscalls/cma/
Dprocess_vm_writev02.c38 #define PADDING_SIZE 10 macro
161 lp = SAFE_MALLOC(tst_exit, bufsz + PADDING_SIZE * 2); in child_write()
163 for (i = 0; i < bufsz + PADDING_SIZE * 2; i++) in child_write()
166 lp[i + PADDING_SIZE] = i % 256; in child_write()
168 local.iov_base = lp + PADDING_SIZE; in child_write()
188 sflag ? SAFE_STRTOL(NULL, sz_opt, 1, LONG_MAX - PADDING_SIZE * 2) in setup()
/third_party/ffmpeg/libavcodec/x86/
Dhevc_sao.asm201 %define PADDING_SIZE 64 ; AV_INPUT_BUFFER_PADDING_SIZE
202 %define EDGE_SRCSTRIDE 2 * MAX_PB_SIZE + PADDING_SIZE
Dhevc_sao_10bit.asm193 %define PADDING_SIZE 64 ; AV_INPUT_BUFFER_PADDING_SIZE
194 %define EDGE_SRCSTRIDE 2 * MAX_PB_SIZE + PADDING_SIZE