Home
last modified time | relevance | path

Searched refs:PIPE_CONTROL_CACHE_INVALIDATE_BITS (Results 1 – 6 of 6) sorted by relevance

/third_party/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.h72 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ macro
Dbrw_pipe_control.c43 (flags & PIPE_CONTROL_CACHE_INVALIDATE_BITS)) { in brw_emit_pipe_control_flush()
/third_party/mesa3d/src/gallium/drivers/crocus/
Dcrocus_pipe_control.c66 (flags & PIPE_CONTROL_CACHE_INVALIDATE_BITS)) { in crocus_emit_pipe_control_flush()
Dcrocus_context.h267 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ macro
/third_party/mesa3d/src/gallium/drivers/iris/
Diris_pipe_control.c63 (flags & PIPE_CONTROL_CACHE_INVALIDATE_BITS)) { in iris_emit_pipe_control_flush()
Diris_context.h349 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ macro