| /third_party/cmsis/CMSIS/DSP/Source/QuaternionMathFunctions/ |
| D | arm_rotation2quaternion_f32.c | 70 #define R11 vgetq_lane(q2,0) macro
98 trace = R00 + R11 + R22; in arm_rotation2quaternion_f32()
115 else if ((R00 > R11) && (R00 > R22) ) in arm_rotation2quaternion_f32()
117 (void)arm_sqrt_f32(1.0 + R00 - R11 - R22,&doubler); // invs=4*qx in arm_rotation2quaternion_f32()
129 else if (R11 > R22) in arm_rotation2quaternion_f32()
131 (void)arm_sqrt_f32(1.0 + R11 - R00 - R22,&doubler); // invs=4*qy in arm_rotation2quaternion_f32()
145 (void)arm_sqrt_f32(1.0 + R22 - R00 - R11,&doubler); // invs=4*qz in arm_rotation2quaternion_f32()
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| /third_party/ffmpeg/libavcodec/arm/ |
| D | simple_idct_arm.S | 63 @@ at this point, R0=block, R14=&block[56], R12=__const_ptr_, R1-R11 free
76 @@ R3=ROWr32[2], R4=ROWr32[3], R5-R11 free
88 @@ R5=(temp), R6=ROWr16[0], R7=ROWr16[1], R8-R11 free,
106 ldr r11, =W7 @ R11=W7
119 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
127 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
159 @@ R5=b2, R6=ROWr16[0], R7=b3, R8 (free), R9 (free), R10 (free), R11 (free),
174 mul r11, r10, r4 @ R11=W6*ROWr16[2]
183 mul r11, r8, r4 @ R11=W2*ROWr16[2]
189 @@ R5=b2, R6=a0, R7=b3, R8=W2, R9=W4, R10=W6, R11 (free),
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 36 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
50 R11)>;
56 R11, CP, DP, SP, LR)> {
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| D | XCoreCallingConv.td | 30 // The 'nest' parameter, if any, is passed in R11.
31 CCIfNest<CCAssignToReg<[R11]>>,
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| D | XCoreInstrInfo.td | 638 let Uses = [R11], isCall=1 in
652 let Defs = [R11], hasSideEffects = 0, isReMaterializable = 1 in
656 let Defs = [R11], isReMaterializable = 1 in
658 [(set R11, (cprelwrapper tglobaladdr:$a))]>;
660 let Defs = [R11] in
685 let Defs = [R11], isReMaterializable = 1 in {
690 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
699 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
703 [(set R11, (pcrelwrapper tblockaddress:$a))]>;
708 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 36 def RR2 : LanaiReg<11, "rr2", [R11]>, DwarfRegAlias<R11>;
50 R10, RR1, R11, RR2, // programmer controlled registers
|
| /third_party/openssl/crypto/sha/asm/ |
| D | keccak1600-avx512vl.pl | 56 my ($R20,$R01,$R31,$R21,$R41,$R11) = map("%ymm$_",(16..21));
110 vprolvq $R11,$A11,@T[1] # $A11 -> future $A01
215 vmovdqa64 5*32(%r8),$R11
301 vmovdqa64 5*32(%r8),$R11
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.td | 122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
266 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
271 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
282 R11, R10, R9, R8,
293 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
317 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
336 // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and
339 def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>;
|
| D | ARMBaseRegisterInfo.h | 51 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
63 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
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| D | Thumb1FrameLowering.cpp | 213 case ARM::R11: in emitPrologue()
275 case ARM::R11: in emitPrologue()
356 case ARM::R11: in emitPrologue()
877 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8}; in spillCalleeSavedRegisters()
986 static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11}; in restoreCalleeSavedRegisters()
|
| /third_party/libunwind/src/x86_64/ |
| D | init.h | 60 c->dwarf.loc[R11] = REG_INIT_LOC(c, r11, R11); in common_init()
|
| D | unwind_i.h | 50 #define R11 11 macro
|
| D | Gregs.c | 116 case UNW_X86_64_R11: loc = c->dwarf.loc[R11]; break; in tdep_access_reg()
|
| /third_party/musl/arch/x86_64/bits/ |
| D | reg.h | 9 #define R11 6 macro
|
| /third_party/musl/arch/x32/bits/ |
| D | reg.h | 9 #define R11 6 macro
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 55 def R11 : AVRReg<11, "r11">, DwarfRegNum<[11]>;
100 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>;
120 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
127 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.cpp | 53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
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| D | MSP430RegisterInfo.td | 64 def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>;
81 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 40 def R11 : Core<11, "%r11">, DwarfRegNum<[11]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineAndOrXor.cpp | 354 Value *R11, *R12; in getMaskedTypeForICmpPair() local
356 if (decomposeBitTestICmp(R1, R2, PredR, R11, R12, R2)) { in getMaskedTypeForICmpPair()
357 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
358 A = R11; in getMaskedTypeForICmpPair()
362 D = R11; in getMaskedTypeForICmpPair()
370 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) { in getMaskedTypeForICmpPair()
373 R11 = R1; in getMaskedTypeForICmpPair()
377 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
378 A = R11; in getMaskedTypeForICmpPair()
384 D = R11; in getMaskedTypeForICmpPair()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 69 case Lanai::R11: in getLanaiRegisterNumbering()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 167 {codeview::RegisterId::R11, X86::R11}, in initLLVMToSEHAndCVRegMapping()
649 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegisterOrZero()
686 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegisterOrZero()
722 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegisterOrZero()
758 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegisterOrZero()
759 return X86::R11; in getX86SubSuperRegisterOrZero()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFRegisterInfo.td | 49 R11, // Stack Ptr
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/MCTargetDesc/ |
| D | BPFMCTargetDesc.cpp | 43 InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */); in createBPFMCRegisterInfo()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 184 ENTRY(R11) \
202 ENTRY(R11) \
|