Home
last modified time | relevance | path

Searched refs:R5 (Results 1 – 25 of 115) sorted by relevance

12345

/third_party/skia/third_party/externals/tint/fuzzers/tint_regex_fuzzer/
Dregex_fuzzer_tests.cc43 R5 = ";regionregionregionregionregion5;"; in TEST() local
44 std::string all_regions = R1 + R2 + R3 + R4 + R5; in TEST()
51 ASSERT_EQ(R1 + R4 + R3 + R2 + R5, all_regions); in TEST()
59 R5 = ";regionregionregionregionregion5;"; in TEST() local
74 R5 = ";regionregionregionregionregion5;"; in TEST() local
75 std::string all_regions = R1 + R2 + R3 + R4 + R5; in TEST()
80 R5.length(), all_regions); in TEST()
82 ASSERT_EQ(R1 + R2 + R3 + R5 + R4, all_regions); in TEST()
89 R5 = ";regionregionregionregionregion5;"; in TEST() local
90 std::string all_regions = R1 + R2 + R3 + R4 + R5; in TEST()
[all …]
/third_party/boost/libs/context/src/asm/
Dontop_ppc32_sysv_elf_gas.S59 # Linux: ontop_fcontext( hidden transfer_t * R3, R4, R5, R6)
60 # Other: transfer_t R3:R4 = jump_fcontext( R3, R4, R5)
187 # Linux: fcontext_ontop_tail( hidden transfer_t * R3, R4, R5, R6, R7)
188 # Other: transfer_t R3:R4 = fcontext_ontop_tail( R3, R4, R5, R6)
Djump_ppc32_sysv_elf_gas.S59 # Linux: jump_fcontext( hidden transfer_t * R3, R4, R5)
/third_party/ffmpeg/libavcodec/arm/
Dsimple_idct_arm.S76 @@ R3=ROWr32[2], R4=ROWr32[3], R5-R11 free
77 orr r5, r4, r3 @ R5=R4 | R3
78 orr r5, r5, r2 @ R5=R4 | R3 | R2
79 orrs r6, r5, r1 @ Test R5 | R1 (the aim is to check if everything is null)
83 orrs r5, r5, r7 @ R5=R4 | R3 | R2 | R7
88 @@ R5=(temp), R6=ROWr16[0], R7=ROWr16[1], R8-R11 free,
107 …mul r5, r10, r7 @ R5=W5*ROWr16[1]=b2 (ROWr16[1] must be the second arg, to have the possi…
114 …mlane r5, r8, r2, r5 @ R5-=W1*ROWr16[3]=b2 (ROWr16[3] must be the second arg, to have the poss…
119 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
127 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
[all …]
/third_party/libdrm/data/
Damdgpu.ids23 6610, 83, AMD Radeon (TM) R5 340
39 6660, 81, AMD Radeon (TM) R5 M335
40 6660, 83, AMD Radeon (TM) R5 M330
42 6663, 83, AMD Radeon (TM) R5 M320
43 6664, 0, AMD Radeon R5 M200 Series
44 6665, 0, AMD Radeon R5 M200 Series
45 6665, 83, AMD Radeon (TM) R5 M320
46 6667, 0, AMD Radeon R5 M200 Series
163 6901, 0, AMD Radeon R5 M255
164 6907, 0, AMD Radeon R5 M255
[all …]
/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/
Dcomc597.mme.h153 MME_INSN(0, ADD, R5, LOAD0, ZERO, 0, NONE, NONE,
158 ADD, ZERO, R5, ZERO, 0, NONE, ALU1),
372 STATE, R5, IMMED, ZERO, 0x1438/4, NONE, NONE),
428 MME_INSN(0, ADD, ZERO, R5, ZERO, 0, NONE, ALU0,
464 ADD, R5, LOAD0, ZERO, 0, NONE, NONE),
473 MME_INSN(0, ADD, ZERO, R5, ZERO, 0, NONE, ALU0,
476 ADD, ZERO, R5, ZERO, 0, NONE, ALU1),
523 ADD, R5, LOAD1, ZERO, 0, NONE, NONE),
525 SUB, R5, R5, R6, 0, NONE, NONE),
526 MME_INSN(0, BLE, ZERO, R5, R7, (2<<14)|0x0002, NONE, NONE,
[all …]
/third_party/icu/icu4c/source/data/mappings/
Dlmb-excp.ucm33 <U005E> \x01\x33 |3 # R5 compatibility
34 <U005E> \x01\x6D |3 # R5 compatibility
36 <U0060> \x01\x34 |3 # R5 compatibility
38 <U007E> \x01\x31 |3 # R5 compatibility
39 <U007E> \x01\x6C |3 # R5 compatibility
43 <U00A8> \x01\x30 |3 # R5 compatibility
46 <U00B4> \x01\x35 |3 # R5 compatibility
115 <U02DA> \x01\x32 |3 # R5 compatibility
116 <U02DA> \x01\x44 |3 # R5 compatibility
/third_party/skia/third_party/externals/icu/source/data/mappings/
Dlmb-excp.ucm33 <U005E> \x01\x33 |3 # R5 compatibility
34 <U005E> \x01\x6D |3 # R5 compatibility
36 <U0060> \x01\x34 |3 # R5 compatibility
38 <U007E> \x01\x31 |3 # R5 compatibility
39 <U007E> \x01\x6C |3 # R5 compatibility
43 <U00A8> \x01\x30 |3 # R5 compatibility
46 <U00B4> \x01\x35 |3 # R5 compatibility
115 <U02DA> \x01\x32 |3 # R5 compatibility
116 <U02DA> \x01\x44 |3 # R5 compatibility
/third_party/flutter/skia/third_party/externals/icu/source/data/mappings/
Dlmb-excp.ucm33 <U005E> \x01\x33 |3 # R5 compatibility
34 <U005E> \x01\x6D |3 # R5 compatibility
36 <U0060> \x01\x34 |3 # R5 compatibility
38 <U007E> \x01\x31 |3 # R5 compatibility
39 <U007E> \x01\x6C |3 # R5 compatibility
43 <U00A8> \x01\x30 |3 # R5 compatibility
46 <U00B4> \x01\x35 |3 # R5 compatibility
115 <U02DA> \x01\x32 |3 # R5 compatibility
116 <U02DA> \x01\x44 |3 # R5 compatibility
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp42 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
47 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
52 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
58 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
DMSP430RegisterInfo.td58 def R5 : MSP430RegWithSubregs<5, "r5", [R5B]>;
81 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td30 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFCallingConv.td22 CCIfType<[i64], CCAssignToReg<[ R1, R2, R3, R4, R5 ]>>,
38 [R1, R2, R3, R4, R5]>>,
41 CCIfType<[i64], CCAssignToRegWithShadow<[R1, R2, R3, R4, R5],
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td33 def FP : LanaiReg< 5, "fp", [R5]>, DwarfRegAlias<R5>;
52 R5, FP, // frame pointer
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp37 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_AlignArgRegs()
62 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
/third_party/icu/icu4j/main/classes/core/src/com/ibm/icu/impl/
DRow.java36 public static <C0, C1, C2, C3, C4> R5<C0,C1,C2,C3,C4> of(C0 p0, C1 p1, C2 p2, C3 p3, C4 p4) { in of()
37 return new R5<>(p0,p1,p2,p3,p4); in of()
55 public static class R5<C0, C1, C2, C3, C4> extends Row<C0, C1, C2, C3, C4> { class in Row
56 public R5(C0 a, C1 b, C2 c, C3 d, C4 e) { in R5() method in Row.R5
/third_party/icu/ohos_icu4j/src/main/java/ohos/global/icu/impl/
DRow.java40 public static <C0, C1, C2, C3, C4> R5<C0,C1,C2,C3,C4> of(C0 p0, C1 p1, C2 p2, C3 p3, C4 p4) { in of()
41 return new R5<>(p0,p1,p2,p3,p4); in of()
71 public static class R5<C0, C1, C2, C3, C4> extends Row<C0, C1, C2, C3, C4> { class in Row
72 public R5(C0 a, C1 b, C2 c, C3 d, C4 e) { in R5() method in Row.R5
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.td122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
266 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
272 R6, R5, R4, (sequence "D%u", 15, 0))>;
281 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
294 R5, R4, (sequence "D%u", 15, 8),
299 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
304 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
317 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
/third_party/ffmpeg/libswscale/x86/
Dyuv_2_rgb.asm194 paddsw m5, m1 ; R1 R3 R5 R7 ...
202 packuswb m0, m3 ; R0 R2 R4 R6 ... R1 R3 R5 R7 ...
209 punpcklbw m6, m_red ; B0 R1 B2 R3 B4 R5 B6 R7 B8 R9 ...
214 punpckhwd m5, m6 ; R4 G4 B4 R5 R6 G6 B6 R7
226 psllq m5, 32 ; -- -- -- -- R4 G4 B4 R5
243 movd [imageq + 12], m5 ; R4 G4 B4 R5
Dinput.asm156 pshufb m3, m2, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
167 movd m3, [srcq+14] ; (byte) { R4, B5, G5, R5 }
171 punpckldq m3, m6 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
176 punpcklbw m3, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
182 pmaddwd m3, coeff2 ; (dword) { R4*RY, G5+GY + R5*RY, R6*RY, G7+GY + R7*RY }
258 movd m5, [srcq+14] ; (byte) { R4, B5, G5, R5 }
270 pshufb m5, m4, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
277 punpckldq m5, m3 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
280 punpcklbw m5, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
284 pmaddwd m3, m5, coeffU2 ; (dword) { R4*BU, G5*GU + R5*BU, R6*BU, G7*GU + R7*BU }
[all …]
/third_party/skia/third_party/externals/libwebp/src/dsp/
Dcommon_sse41.h41 __m128i R0, R1, R2, R3, R4, R5; in VP8PlanarTo24b_SSE41() local
87 const __m128i RG5 = _mm_or_si128(R5, G5); in VP8PlanarTo24b_SSE41()
/third_party/flutter/skia/third_party/externals/libwebp/src/dsp/
Dcommon_sse41.h41 __m128i R0, R1, R2, R3, R4, R5; in VP8PlanarTo24b_SSE41() local
87 const __m128i RG5 = _mm_or_si128(R5, G5); in VP8PlanarTo24b_SSE41()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.td49 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
103 def R5R4 : AVRReg<4, "r5:r4", [R4, R5]>, DwarfRegNum<[4]>;
121 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
127 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCRegisterInfo.td34 def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h54 case Lanai::R5: in getLanaiRegisterNumbering()

12345