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Searched refs:REV16 (Results 1 – 16 of 16) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedCyclone.td149 // CLS,CLZ,RBIT,REV,REV16,REV32
499 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
DAArch64ISelLowering.h107 REV16, enumerator
DAArch64SchedFalkorDetails.td1207 def : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>;
DAArch64ISelLowering.cpp1285 case AArch64ISD::REV16: return "AArch64ISD::REV16"; in getTargetNodeName()
7083 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
7300 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
DAArch64InstrInfo.td454 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
3774 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleR52.td338 (instregex "t2LDC", "RBIT", "REV", "REV16", "REVSH", "RRX")>;
DARMScheduleSwift.td131 // CLZ,RBIT,REV,REV16,REVSH,PKH
DARMInstrInfo.td4555 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4562 (REV16 (LDRH addrmode3:$addr))>;
4564 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
DARMInstrThumb2.td4945 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmWriter.inc2370 3172683U, // REV16
6594 16384U, // REV16
DARMGenMCCodeEmitter.inc1678 UINT64_C(113184688), // REV16
13126 case ARM::REV16:
18353 CEFBS_IsARM_HasV6, // REV16 = 1665
DARMGenDAGISel.inc28478 /* 60648*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::REV16), 0,
28481 // Dst: (REV16:{ *:[i32] } (LDRH:{ *:[i32] } addrmode3:{ *:[i32] }:$addr))
28617 /* 60972*/ OPC_EmitNode1, TARGET_VAL(ARM::REV16), 0,
28624 … // Dst: (STRH (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rn), addrmode3:{ *:[i32] }:$addr)
41259 /* 89495*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::REV16), 0,
41262 // Dst: (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
DARMGenInstrInfo.inc1680 REV16 = 1665,
7511 …CID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1665 = REV16
DARMGenAsmMatcher.inc10982 …{ 865 /* rev16 */, ARM::REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_Cond…
DARMGenDisassemblerTables.inc1307 /* 5970 */ MCD::OPC_Decode, 129, 13, 35, // Opcode: REV16
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenFastISel.inc1370 // FastEmit functions for AArch64ISD::REV16.
4714 case AArch64ISD::REV16: return fastEmit_AArch64ISD_REV16_r(VT, RetVT, Op0, Op0IsKill);