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Searched refs:RL (Results 1 – 25 of 48) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Remarks/
DYAMLRemarkSerializer.cpp24 Optional<RemarkLocation> RL, T FunctionName, in mapRemarkHeader() argument
29 io.mapOptional("DebugLoc", RL); in mapRemarkHeader()
77 static void mapping(IO &io, RemarkLocation &RL) { in mapping()
80 StringRef File = RL.SourceFilePath; in mapping()
81 unsigned Line = RL.SourceLine; in mapping()
82 unsigned Col = RL.SourceColumn; in mapping()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonBlockRanges.cpp75 void HexagonBlockRanges::RangeList::include(const RangeList &RL) { in include() argument
76 for (auto &R : RL) in include()
442 RangeList &RL = F->second; in computeDeadMap() local
443 RangeList::iterator A = RL.begin(), Z = RL.end()-1; in computeDeadMap()
514 const HexagonBlockRanges::RangeList &RL) { in operator <<() argument
515 for (auto &R : RL) in operator <<()
532 const HexagonBlockRanges::RangeList &RL = I.second; in operator <<() local
533 OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; in operator <<()
DHexagonBlockRanges.h114 void include(const RangeList &RL);
238 const HexagonBlockRanges::RangeList &RL);
DHexagonFrameLowering.cpp2188 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B]; in optimizeSpillSlots() local
2190 RL.add(LastStore[FI], LastLoad[FI], false, false); in optimizeSpillSlots()
2192 RL.add(IndexType::Entry, LastLoad[FI], false, false); in optimizeSpillSlots()
2205 auto &RL = FIRangeMap[I.first].Map[&B]; in optimizeSpillSlots() local
2208 RL.add(LS, LL, false, false); in optimizeSpillSlots()
2210 RL.add(IndexType::Entry, LL, false, false); in optimizeSpillSlots()
2217 auto &RL = FIRangeMap[I.first].Map[&B]; in optimizeSpillSlots() local
2218 RL.add(LS, IndexType::None, false, false); in optimizeSpillSlots()
2295 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B]; in optimizeSpillSlots() local
2296 for (auto &Range : RL) { in optimizeSpillSlots()
[all …]
DHexagonGenInsert.cpp420 : RL(L), TRI(RI) {} in PrintORL()
425 const OrderedRegisterList &RL; member
431 OrderedRegisterList::const_iterator B = P.RL.begin(), E = P.RL.end(); in operator <<()
/third_party/mbedtls/library/
DMakefile63 RL ?= ranlib macro
212 $(RL) $(RLFLAGS) $@
239 $(RL) $(RLFLAGS) $@
266 $(RL) $(RLFLAGS) $@
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyExplicitLocals.cpp379 auto RL = Reg2Local.find(Reg); in runOnMachineFunction() local
380 if (RL == Reg2Local.end() || RL->second < MFI.getParams().size()) in runOnMachineFunction()
383 MFI.setLocal(RL->second - MFI.getParams().size(), in runOnMachineFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.td37 def RL#i : NVPTXReg<"%rd"#i>; // 64-bit
60 def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 4))>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp506 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
509 GetSplitOp(N->getOperand(2), RL, RH); in SplitRes_SELECT()
538 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL); in SplitRes_SELECT()
544 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
547 GetSplitOp(N->getOperand(3), RL, RH); in SplitRes_SELECT_CC()
550 N->getOperand(1), LL, RL, N->getOperand(4)); in SplitRes_SELECT_CC()
DLegalizeIntegerTypes.cpp2910 SDValue LL, LH, RL, RH; in ExpandIntRes_Logical() local
2912 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_Logical()
2913 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); in ExpandIntRes_Logical()
2923 SDValue LL, LH, RL, RH; in ExpandIntRes_MUL() local
2925 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_MUL()
2929 LL, LH, RL, RH)) in ExpandIntRes_MUL()
2953 SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask); in ExpandIntRes_MUL()
2967 SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift); in ExpandIntRes_MUL()
2987 DAG.getNode(ISD::MUL, dl, NVT, RL, LH))); in ExpandIntRes_MUL()
3070 SDValue LL, LH, RL, RH; in ExpandIntRes_MULFIX() local
[all …]
/third_party/python/Tools/msi/bundle/bootstrap/
Dpythonba.def4 ; This software is released under Microsoft Reciprocal License (MS-RL).
DLICENSE.txt5 Microsoft Reciprocal License (MS-RL)
/third_party/alsa-lib/src/conf/pcm/
Dsurround50.conf58 ttable.2.RL 1
Dsurround41.conf58 ttable.2.RL 1
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ADT/
DImmutableSet.h516 TreeTy *RL = getLeft(R); in balanceTree() local
519 if (getHeight(RR) >= getHeight(RL)) in balanceTree()
520 return createNode(createNode(L,V,RL), R, RR); in balanceTree()
522 assert(!isEmpty(RL) && "RL cannot be empty because it has a height >= 1"); in balanceTree()
524 TreeTy *RLL = getLeft(RL); in balanceTree()
525 TreeTy *RLR = getRight(RL); in balanceTree()
527 return createNode(createNode(L,V,RLL), RL, createNode(RLR,R,RR)); in balanceTree()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZScheduleZ196.td176 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
177 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
192 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
194 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
220 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
222 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
242 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
271 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LA(Y|RL)?$")>;
484 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "C(G|Y|Mux|RL)?$")>;
487 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
[all …]
DSystemZScheduleZEC12.td181 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
182 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
200 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
202 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
228 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
230 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
253 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
282 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LA(Y|RL)?$")>;
495 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "C(G|Y|Mux|RL)?$")>;
498 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
[all …]
DSystemZScheduleZ13.td197 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
220 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
222 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
251 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
253 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
279 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
308 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LA(Y|RL)?$")>;
526 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
543 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
[all …]
DSystemZScheduleZ14.td198 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
200 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
221 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
223 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
252 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
254 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
280 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
309 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LA(Y|RL)?$")>;
536 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
553 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
[all …]
DSystemZScheduleZ15.td199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
201 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
222 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
224 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
256 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
258 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
284 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
313 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LA(Y|RL)?$")>;
550 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
567 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
[all …]
/third_party/ltp/testcases/kernel/fs/acl/
Dtacl_xattr.sh666 getfacl -RL tacl/mount-ext2/ > tacl/tmp1
669 getfacl -RL tacl/mount-ext2/ > tacl/tmp2
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp647 SDValue LL, RL, AddendL, AddendH; in TryExpandADDWithMul() local
650 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in TryExpandADDWithMul()
664 AddendL, LL, RL); in TryExpandADDWithMul()
672 AddendL, LL, RL); in TryExpandADDWithMul()
683 AddendL, LL, RL); in TryExpandADDWithMul()
686 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL); in TryExpandADDWithMul()
/third_party/openssl/doc/man3/
DEVP_CIPHER_meth_new.pod157 explanation or they get removed. /RL
/third_party/boost/libs/wave/test/testwave/testfiles/
Dt_5_035.hpp710 #define RL macro
/third_party/gstreamer/gstplugins_base/ext/alsa/
Dgstalsa.c730 ITEM (RL, REAR_LEFT),

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