| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize() local
128 Size = alignTo(Size + RegSize, RegSize); in estimateStackSize()
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| D | MipsCallLowering.cpp | 505 unsigned RegSize = 4; in lowerFormalArguments() local
507 VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize); in lowerFormalArguments()
511 (int)(RegSize * (ArgRegs.size() - Idx)); in lowerFormalArguments()
515 int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
518 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { in lowerFormalArguments()
522 MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I])); in lowerFormalArguments()
523 FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
528 MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, RegSize, in lowerFormalArguments()
529 /* Alignment */ RegSize); in lowerFormalArguments()
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| D | MipsSEFrameLowering.cpp | 78 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
80 unsigned MFLoOpc, unsigned RegSize);
198 unsigned RegSize) { in expandLoadACC() argument
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
223 unsigned RegSize) { in expandStoreACC() argument
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC()
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 137 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg() local
143 SmallBitVector Coverage(RegSize, false); in addMachineReg()
154 SmallBitVector CurSubReg(RegSize, false); in addMachineReg()
175 if (CurPos < RegSize) in addMachineReg()
176 DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"}); in addMachineReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate() argument
216 (RegSize != 64 && in processLogicalImmediate()
217 (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) in processLogicalImmediate()
221 unsigned Size = RegSize; in processLogicalImmediate()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 482 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0; in getRegSizeInBits() local
485 if (RegSize) in getRegSizeInBits()
486 return RegSize; in getRegSizeInBits()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 233 unsigned RegSize, SpillSize, SpillAlignment; member
272 return getRegClassInfo(RC).RegSize; in getRegSizeInBits()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 914 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} in LogicOp()
916 explicit operator bool() const { return RegSize; } in operator bool()
918 unsigned RegSize = 0; member
963 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); in convertToThreeAddress()
965 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { in convertToThreeAddress()
967 if (And.RegSize == 64) { in convertToThreeAddress()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1703 unsigned RegSize; in emitLogicalOp_ri() local
1714 RegSize = 32; in emitLogicalOp_ri()
1720 RegSize = 64; in emitLogicalOp_ri()
1724 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize)) in emitLogicalOp_ri()
1729 AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitLogicalOp_ri()
4124 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4171 unsigned ImmR = RegSize - Shift; in emitLSL_ri()
4231 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4279 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4352 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
[all …]
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| D | AArch64FrameLowering.cpp | 2405 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
2408 SVECSStackSize += RegSize; in determineCalleeSaves()
2410 CSStackSize += RegSize; in determineCalleeSaves()
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| D | AArch64InstructionSelector.cpp | 3295 unsigned RegSize = MRI.getType(LHS).getSizeInBits(); in emitTST() local
3296 bool Is32Bit = (RegSize == 32); in emitTST()
3305 AArch64_AM::isLogicalImmediate(ValAndVReg->Value, RegSize); in emitTST()
3311 AArch64_AM::encodeLogicalImmediate(ValAndVReg->Value, RegSize)); in emitTST()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 190 int RegSize; in sizeOfSPAdjustment() local
193 RegSize = 8; in sizeOfSPAdjustment()
197 RegSize = 4; in sizeOfSPAdjustment()
210 count += RegSize; in sizeOfSPAdjustment()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 136 unsigned RegSize = RegTy.getSizeInBits(); in extractParts() local
138 unsigned NumParts = RegSize / MainSize; in extractParts()
139 unsigned LeftoverSize = RegSize - NumParts * MainSize; in extractParts()
165 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; in extractParts()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 807 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments() local
808 assert(RegSize == 32 || RegSize == 64 || in LowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 849 unsigned RegSize = RegisterVT.getScalarSizeInBits(); in getCopyFromRegs() local
853 if (NumZeroBits == RegSize) { in getCopyFromRegs()
866 FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits); in getCopyFromRegs()
870 EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1); in getCopyFromRegs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 5078 unsigned RegSize = TRI.getRegSizeInBits(*RC); in isNonFoldablePartialRegisterLoad() local
5083 RegSize > 32) { in isNonFoldablePartialRegisterLoad()
5137 RegSize > 64) { in isNonFoldablePartialRegisterLoad()
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| D | X86ISelLowering.cpp | 36723 unsigned RegSize = std::max(128u, (unsigned)InVT.getSizeInBits()); in createPSADBW() local
36727 unsigned NumConcat = RegSize / InVT.getSizeInBits(); in createPSADBW()
36730 MVT ExtendedVT = MVT::getVectorVT(MVT::i8, RegSize / 8); in createPSADBW()
36741 MVT SadVT = MVT::getVectorVT(MVT::i64, RegSize / 64); in createPSADBW()
36966 unsigned RegSize = 128; in combineBasicSADPattern() local
36968 RegSize = 512; in combineBasicSADPattern()
36970 RegSize = 256; in combineBasicSADPattern()
36975 if (RegSize / VT.getVectorNumElements() < 8) in combineBasicSADPattern()
44847 unsigned RegSize = 128; in combineLoopSADPattern() local
44849 RegSize = 512; in combineLoopSADPattern()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | Target.td | 61 int RegSize = RS; // Register size in bits.
|