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Searched refs:Rm (Results 1 – 25 of 45) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb.td391 let Inst{6-3} = 0b1111; // Rm = pc
450 // ADD <Rm>, sp
462 // ADD sp, <Rm>
463 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
464 "add", "\t$Rdn, $Rm", []>,
467 bits<4> Rm;
469 let Inst{6-3} = Rm;
480 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
483 bits<4> Rm;
484 let Inst{6-3} = Rm;
[all …]
DARMInstrThumb2.td352 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
358 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
517 bits<4> Rm;
520 let Inst{3-0} = Rm;
527 bits<4> Rm;
530 let Inst{3-0} = Rm;
537 bits<4> Rm;
540 let Inst{3-0} = Rm;
576 bits<4> Rm;
580 let Inst{3-0} = Rm;
[all …]
DARMInstrInfo.td1412 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1413 iir, opc, "\t$Rd, $Rn, $Rm",
1414 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1418 bits<4> Rm;
1424 let Inst{3-0} = Rm;
1485 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1486 iir, opc, "\t$Rd, $Rn, $Rm",
1491 bits<4> Rm;
1494 let Inst{3-0} = Rm;
1547 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
[all …]
DARMInstrNEON.td627 let Rm = 0b1111;
635 let Rm = 0b1111;
656 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
661 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
662 "vld1", Dt, "$Vd, $Rn, $Rm",
673 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
678 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
679 "vld1", Dt, "$Vd, $Rn, $Rm",
700 let Rm = 0b1111;
709 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
[all …]
DARMSchedule.td17 // Rd <- ADD Rn, Rm, <shift> Rs
19 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
22 // Rd after a minimum of three cycles after the result in Rm and Rs is available
27 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
DARMInstrFormats.td792 // {11-0} imm12/Rm
810 // {11-0} imm12/Rm
829 // {13} 1 == Rm, 0 == imm12
831 // {11-0} imm12/Rm
849 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
856 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
881 // {13} 1 == imm8, 0 == Rm
885 // {3-0} imm3_0/Rm
907 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
914 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenGlobalISel.inc1320 …d_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, ar…
1324 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm
1334 …arith_shifted_reg32:{ *:[i32] }:$Rm) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted…
1338 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm
1348 …R32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:…
1597 …i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32]…
1601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1626 …i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32]…
1630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1655 …(sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR3…
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td47 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
49 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
50 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
52 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
62 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
64 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
65 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
67 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
77 def : Pat<(relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
79 (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
[all …]
DAArch64InstrFormats.td1494 : AuthBase<M, (outs), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rn, $Rm", []> {
1496 bits<5> Rm;
1500 let Inst{4-0} = Rm;
1806 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64sp:$Rm),
1807 asm, "\t$Rd, $Rn, $Rm", "",
1808 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
1812 bits<5> Rm;
1814 let Inst{20-16} = Rm;
1850 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1851 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
[all …]
DAArch64InstrInfo.td801 def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot90 (v4f16 V64:$Rn), (v4f16 V64:$Rm))),
802 (FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 0))>;
803 def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot270 (v4f16 V64:$Rn), (v4f16 V64:$Rm))),
804 (FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 1))>;
805 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot90 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
806 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 0))>;
807 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot270 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
808 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 1))>;
811 def : Pat<(v2f32 (int_aarch64_neon_vcadd_rot90 (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
812 (FCADDv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm), (i32 0))>;
[all …]
DSVEInstrFormats.td1062 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
1063 asm, "\t$Zdn, $Rm",
1066 bits<5> Rm;
1071 let Inst{9-5} = Rm;
4015 : I<(outs), (ins rt:$Rn, rt:$Rm),
4016 asm, "\t$Rn, $Rm",
4019 bits<5> Rm;
4024 let Inst{20-16} = Rm;
4036 : I<(outs pprty:$Pd), (ins gprty:$Rn, gprty:$Rm),
4037 asm, "\t$Pd, $Rn, $Rm",
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1453 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegImmOperand() local
1458 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegImmOperand()
1490 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegRegOperand() local
1495 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegRegOperand()
1829 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode2IdxInstruction() local
1891 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1933 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegMemOperand() local
1959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegMemOperand()
1978 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode3Instruction() local
2011 if (type && Rm == 15) in DecodeAddrMode3Instruction()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenMCPseudoLowering.inc62 // Operand: Rm
85 // Operand: Rm
106 // Operand: Rm
133 // Operand: Rm
166 // Operand: Rm
209 // Operand: Rm
233 // Operand: Rm
266 // Operand: Rm
341 // Operand: Rm
356 // Operand: Rm
[all …]
DARMGenDAGISel.inc64 /* 18*/ OPC_RecordChild0, // #0 = $Rm
87 …l:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i3…
88 // Dst: (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
95 …{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32…
96 // Dst: (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
102 /* 93*/ OPC_RecordChild0, // #0 = $Rm
125 …l:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i3…
126 // Dst: (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
133 …{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32…
134 // Dst: (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
[all …]
DARMGenGlobalISel.inc919 …32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:…
923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
943 …2] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *…
947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
967 …} rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *…
971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
991 … rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ …
995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1015 …and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn…
1019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
[all …]
DARMGenMCCodeEmitter.inc5299 // op: Rm
5341 // op: Rm
5375 // op: Rm
5391 // op: Rm
6140 // op: Rm
6223 // op: Rm
6248 // op: Rm
6261 // op: Rm
6278 // op: Rm
6298 // op: Rm
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp334 IValueT encodeShiftRotateImm5(IValueT Rm, OperandARM32::ShiftKind Shift, in encodeShiftRotateImm5() argument
338 return (imm5 << kShiftImmShift) | (encodeShift(Shift) << kShiftShift) | Rm; in encodeShiftRotateImm5()
343 IValueT encodeShiftRotateReg(IValueT Rm, OperandARM32::ShiftKind Shift, in encodeShiftRotateReg() argument
346 (Rm << kRmShift); in encodeShiftRotateReg()
389 IValueT Rm; in encodeOperand() local
390 if (encodeOperand(FlexReg->getReg(), Rm, WantGPRegs) != EncodedAsRegister) in encodeOperand()
396 Value = encodeShiftRotateReg(Rm, FlexReg->getShiftOp(), Rs); in encodeOperand()
410 Value = encodeShiftRotateImm5(Rm, FlexReg->getShiftOp(), Imm5); in encodeOperand()
985 RegARM32::GPRRegister Rm = getGPRReg(kRmShift, Address); in emitMemOp() local
989 verifyRegNotPc(Rm, "Rm", InstName); in emitMemOp()
[all …]
DIceAssemblerX8664.h964 const RmType Rm, const AsmAddress *Addr = nullptr) {
972 : (Rm & 0x08) ? AsmOperand::RexB
978 (Addr == nullptr && is8BitRegisterRequiringRex(TyRm, Rm))) {
986 void emitRexRB(const Type Ty, const RegType Reg, const RmType Rm) { in emitRexRB() argument
987 assembleAndEmitRex(Ty, Reg, Ty, Rm); in emitRexRB()
992 const RmType Rm) { in emitRexRB() argument
993 assembleAndEmitRex(TyReg, Reg, TyRm, Rm); in emitRexRB()
999 template <typename RmType> void emitRexB(const Type Ty, const RmType Rm) { in emitRexB() argument
1000 emitRexRB(Ty, RexRegIrrelevant, Ty, Rm); in emitRexB()
DIceAssemblerARM32.h199 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
785 void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm,
791 void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm,
797 IValueT Rm);
813 IValueT Rm, IValueT Rs, bool SetFlags);
/third_party/mbedtls/tests/data_files/dir4/
Dcert74.crt14 2rj5GmpubDXEWAKfMtt0ccF2UIva9rDMNzaAnCSevWHXf9Httr84X6RmhtXb9/Rm
/third_party/openssl/test/certs/
Dbadalt8-key.pem5 PQPxnY2uLSRcMZ7n6FuAs+Rm+eHS+8kKTsARDaKo7g2l7i4egPHcZc2jYlvoEo1/
/third_party/skia/third_party/externals/opengl-registry/extensions/EXT/
DEXT_texture_compression_astc_decode_mode.txt245 int Rm = (Cr & 0x3FF) | (Re == 0 ? 0 : 0x400);
248 Rm = (Rm >> rshift) & 0x1FF;
252 uint32_t texel = (expo << 27) | (Bm << 18) | (Gm << 9) | (Rm << 0);
/third_party/openGLES/extensions/EXT/
DEXT_texture_compression_astc_decode_mode.txt245 int Rm = (Cr & 0x3FF) | (Re == 0 ? 0 : 0x400);
248 Rm = (Rm >> rshift) & 0x1FF;
252 uint32_t texel = (expo << 27) | (Bm << 18) | (Gm << 9) | (Rm << 0);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp938 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeThreeAddrSRegInstruction() local
966 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
987 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1509 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeAddSubERegInstruction() local
1523 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1529 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1535 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1541 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1547 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1553 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
/third_party/boost/libs/graph/doc/
Dmath.sty17 \DeclareMathOperator{\Rm}{R_M}

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