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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPatterns.td46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
241 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
242 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>;
315 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
316 (MI RsPred:$Rs, RtPred:$Rt)>;
325 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
326 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
672 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
673 (Output RsPred:$Rs, RtPred:$Rt)>;
676 : OutPatFrag<(ops node:$Rs, node:$Rt),
[all …]
DHexagonPatternsHVX.td99 def: Pat<(ResType (Load I32:$Rt)),
100 (MI I32:$Rt, 0)>;
101 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
102 (MI I32:$Rt, imm:$s)>;
115 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
116 (MI I32:$Rt, 0)>;
117 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
118 (MI I32:$Rt, imm:$Off)>;
141 def: Pat<(Store Value:$Vs, I32:$Rt),
142 (MI I32:$Rt, 0, Value:$Vs)>;
[all …]
DHexagonIntrinsics.td16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
27 def: Pat<(int_hexagon_A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt),
28 (A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
30 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
31 (A2_sub IntRegs:$Rs, IntRegs:$Rt)>;
[all …]
DHexagonPatternsV65.td12 (ins IntRegs:$_dst_, IntRegs:$Rt,
21 (ins IntRegs:$_dst_, IntRegs:$Rt,
30 (ins IntRegs:$_dst_, IntRegs:$Rt,
43 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
52 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
61 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
DHexagonAsmPrinter.cpp374 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
375 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
376 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
381 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
385 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
386 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
387 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
392 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
397 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
398 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
[all …]
DHexagonIntrinsicsV5.td41 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
45 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
50 // Rdd=vpmpyh(Rs,Rt)
52 // Rxx[^]=vpmpyh(Rs,Rt)
56 // Rdd=pmpyw(Rs,Rt)
58 // Rxx^=pmpyw(Rs,Rt)
61 //Rxx^=asr(Rss,Rt)
63 //Rxx^=asl(Rss,Rt)
65 //Rxx^=lsr(Rss,Rt)
67 //Rxx^=lsl(Rss,Rt)
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td1170 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
1171 opc, ".w\t$Rt, $addr",
1172 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>,
1174 bits<4> Rt;
1182 let Inst{15-12} = Rt;
1187 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
1188 opc, "\t$Rt, $addr",
1189 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>,
1191 bits<4> Rt;
1200 let Inst{15-12} = Rt;
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DARMInstrInfo.td1872 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1873 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1874 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1875 bits<4> Rt;
1879 let Inst{15-12} = Rt;
1882 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1883 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1884 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1885 bits<4> Rt;
1890 let Inst{15-12} = Rt;
[all …]
DARMInstrVFP.td1072 (outs GPR:$Rt), (ins SPR:$Sn),
1073 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
1074 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>,
1078 bits<4> Rt;
1084 let Inst{15-12} = Rt;
1096 (outs SPR:$Sn), (ins GPR:$Rt),
1097 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
1098 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
1103 bits<4> Rt;
1108 let Inst{15-12} = Rt;
[all …]
DARMInstrThumb.td671 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
672 "ldr", "\t$Rt, $addr",
673 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
676 bits<3> Rt;
678 let Inst{10-8} = Rt;
685 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
686 "ldr", "\t$Rt, $addr",
687 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
689 bits<3> Rt;
691 let Inst{10-8} = Rt;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp676 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
680 if (Rs >= Rt) { in DecodeAddiGroupBranch()
683 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
694 Rt))); in DecodeAddiGroupBranch()
704 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
708 if (Rs >= Rt) { in DecodePOP35GroupBranchMMR6()
711 Rt))); in DecodePOP35GroupBranchMMR6()
715 } else if (Rs != 0 && Rs < Rt) { in DecodePOP35GroupBranchMMR6()
720 Rt))); in DecodePOP35GroupBranchMMR6()
725 Rt))); in DecodePOP35GroupBranchMMR6()
[all …]
/third_party/openGLES/extensions/EXT/
DEXT_texture.txt232 Texture components are assigned to Rt, Gt, Bt, and At.
239 Base Texture Format Rt Gt Bt At
250 RGB Rt Gt Bt x
252 RGBA Rt Gt Bt At
254 Table ??: Mapping of Texture Components to Rt, Gt, Bt, At.
271 … LUMINANCE Rv = Rt Rv = Rf * Rt Rv = Rf * (1-Rt) + Rc * Rt undefined
281 … INTENSITY_EXT Rv = Rt Rv = Rf * Rt Rv = Rf * (1-Rt) + Rc * Rt undefined
286 … LUMINANCE_ALPHA Rv = Rt Rv = Rf * Rt Rv = Rf * (1-Rt) + Rc * Rt undefined
291 … RGB Rv = Rt Rv = Rf * Rt Rv = Rf * (1-Rt) + Rc * Rt Rv = Rt
296 …RGBA Rv = Rt Rv = Rf * Rt Rv = Rf * (1-Rt) + Rc * Rt Rv = Rf * …
DEXT_texture_env.txt218 RGB Rf Rt Rf*Rt Rf+Rt
223 RGBA Rf Rt Rf*Rt Rf+Rt
253 RGB Rf-Rt Rt-Rf Af*Rf+(1-Af)*Rt Af*Rt+(1-Af)*Rf
258 RGBA Rf-Rt Rt-Rf Af*Rf+(1-Af)*Rt Af*Rt+(1-Af)*Rf
298 fragment; Rt, Gt, Bt, At, Lt, and It are the filtered texture values; Rc,
374 texture environment, the filtered texture values Rt, Gt, Bt, At, Lt, and
/third_party/skia/third_party/externals/opengl-registry/extensions/EXT/
DEXT_texture.txt232 Texture components are assigned to Rt, Gt, Bt, and At.
239 Base Texture Format Rt Gt Bt At
250 RGB Rt Gt Bt x
252 RGBA Rt Gt Bt At
254 Table ??: Mapping of Texture Components to Rt, Gt, Bt, At.
271 … LUMINANCE Rv = Rt Rv = Rf * Rt Rv = Rf * (1-Rt) + Rc * Rt undefined
281 … INTENSITY_EXT Rv = Rt Rv = Rf * Rt Rv = Rf * (1-Rt) + Rc * Rt undefined
286 … LUMINANCE_ALPHA Rv = Rt Rv = Rf * Rt Rv = Rf * (1-Rt) + Rc * Rt undefined
291 … RGB Rv = Rt Rv = Rf * Rt Rv = Rf * (1-Rt) + Rc * Rt Rv = Rt
296 …RGBA Rv = Rt Rv = Rf * Rt Rv = Rf * (1-Rt) + Rc * Rt Rv = Rf * …
DEXT_texture_env.txt218 RGB Rf Rt Rf*Rt Rf+Rt
223 RGBA Rf Rt Rf*Rt Rf+Rt
253 RGB Rf-Rt Rt-Rf Af*Rf+(1-Af)*Rt Af*Rt+(1-Af)*Rf
258 RGBA Rf-Rt Rt-Rf Af*Rf+(1-Af)*Rt Af*Rt+(1-Af)*Rf
298 fragment; Rt, Gt, Bt, At, Lt, and It are the filtered texture values; Rc,
374 texture environment, the filtered texture values Rt, Gt, Bt, At, Lt, and
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp200 MCOperand Rs, Rt; in getCompoundInsn() local
210 Rt = L.getOperand(0); in getCompoundInsn()
215 CompoundInsn->addOperand(Rt); in getCompoundInsn()
221 Rt = L.getOperand(0); in getCompoundInsn()
227 CompoundInsn->addOperand(Rt); in getCompoundInsn()
236 Rt = L.getOperand(2); in getCompoundInsn()
242 CompoundInsn->addOperand(Rt); in getCompoundInsn()
249 Rt = L.getOperand(2); in getCompoundInsn()
255 CompoundInsn->addOperand(Rt); in getCompoundInsn()
262 Rt = L.getOperand(2); in getCompoundInsn()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.cpp210 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRsRt() local
213 Opcode |= Rt << 16; in emitRsRt()
221 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16() local
225 Opcode |= Rt << 16; in emitRtRsImm16()
236 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16Rel() local
249 Opcode |= Rt << 16; in emitRtRsImm16Rel()
272 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRdRtSa() local
274 Opcode |= Rt << 16; in emitRdRtSa()
286 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRdRsRt() local
289 Opcode |= Rt << 16; in emitRdRsRt()
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DIceAssemblerARM32.cpp935 bool IsLoad, bool IsByte, IValueT Rt, in emitMemOp() argument
937 assert(Rt < RegARM32::getNumGPRegs()); in emitMemOp()
941 (IsByte ? B : 0) | (Rt << kRdShift) | Address; in emitMemOp()
946 IValueT Rt, const Operand *OpAddress, in emitMemOp() argument
973 emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address); in emitMemOp()
991 verifyRegNotPc(Rt, "Rt", InstName); in emitMemOp()
994 verifyRegsNotEq(Rn, "Rn", Rt, "Rt", InstName); in emitMemOp()
996 emitMemOp(Cond, kInstTypeRegisterShift, IsLoad, IsByte, Rt, Address); in emitMemOp()
1003 IValueT Rt, const Operand *OpAddress, in emitMemOpEnc3() argument
1020 assert(Rt < RegARM32::getNumGPRegs()); in emitMemOpEnc3()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1031 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
1042 Inst.addOperand(MCOperand::createImm(Rt)); in DecodeUnsignedLdStInstruction()
1052 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1059 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1063 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1067 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1071 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1075 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1079 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1092 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1008 [(set GPR64:$Rt, (int_aarch64_tstart))]>;
1015 def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]> {
1460 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
1493 def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">;
1497 def : Pat<(int_aarch64_ldg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$offset)),
1498 (LDG GPR64:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
1500 def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;
1502 def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",
1503 (outs GPR64:$Rt), (ins GPR64sp:$Rn)>;
1504 def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
[all …]
DAArch64InstrFormats.td1167 // System instructions which do not have an Rt register.
1174 // System instructions which have an Rt register.
1178 bits<5> Rt;
1179 let Inst{4-0} = Rt;
1199 (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> {
1200 bits<5> Rt;
1201 let Inst{4-0} = Rt;
1321 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
1322 "mrs", "\t$Rt, $systemreg"> {
1330 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
[all …]
/third_party/skia/third_party/externals/opengl-registry/extensions/SGI/
DSGI_texture_color_table.txt71 to Rt, Gt, Bt, At and now the table is always applied to all 4
164 Rt, Gt, Bt, and At according to the following table:
170 Internal Format Rt Gt Bt At
173 ALPHA Rt Gt Bt A(At)
175 LUMINANCE L(Rt) L(Gt) L(Bt) At
177 LUMINANCE_ALPHA L(Rt) L(Gt) L(Bt) A(At)
179 INTENSITY I(Rt) I(Gt) I(Bt) I(At)
181 RGB R(Rt) G(Gt) B(Bt) At
183 RGBA R(Rt) G(Gt) B(Bt) A(At)
/third_party/openGLES/extensions/SGI/
DSGI_texture_color_table.txt71 to Rt, Gt, Bt, At and now the table is always applied to all 4
164 Rt, Gt, Bt, and At according to the following table:
170 Internal Format Rt Gt Bt At
173 ALPHA Rt Gt Bt A(At)
175 LUMINANCE L(Rt) L(Gt) L(Bt) At
177 LUMINANCE_ALPHA L(Rt) L(Gt) L(Bt) A(At)
179 INTENSITY I(Rt) I(Gt) I(Bt) I(At)
181 RGB R(Rt) G(Gt) B(Bt) At
183 RGBA R(Rt) G(Gt) B(Bt) A(At)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1828 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
1853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1887 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1976 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
1985 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction()
1997 if (Rt & 0x1) S = MCDisassembler::SoftFail; in DecodeAddrMode3Instruction()
2009 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2021 if (Rt == 15) in DecodeAddrMode3Instruction()
2023 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
2038 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
[all …]
/third_party/boost/boost/units/
Ddimension.hpp70 template<typename DL,typename Rt>
75 Rt

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