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Searched refs:SALU (Results 1 – 12 of 12) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td17 field bit SALU = 0;
20 // SALU instruction formats.
131 let TSFlags{0} = SALU;
218 let SALU = 1;
DSIInstrInfo.h334 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
338 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
599 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD); in isScalarUnit()
DSIDefines.h21 SALU = 1 << 0, enumerator
DSOPInstructions.td47 let SALU = 1;
334 let SALU = 1;
618 let SALU = 1;
854 let SALU = 1;
956 let SALU = 1;
983 let SALU = 1;
DSISchedule.td55 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
DSIInstructions.td189 } // End let usesCustomInserter = 1, SALU = 1
339 let SALU = 1;
1092 let AddedComplexity = 1 in { // Prefer SALU to VALU patterns for DAG
/third_party/mesa3d/src/amd/compiler/
DREADME-ISA.md214 Then, a SALU/SMEM instruction writes the same SGPR.
225 Any non-SOPP SALU instruction (except `s_setvskip`, `s_version`, and any non-lgkmcnt `s_waitcnt`).
/third_party/mesa3d/docs/relnotes/
D20.1.0.rst3496 - aco: improve SCC handling in some SALU combines
3574 - aco: combine VALU and SALU into various VOP3 instructions
D21.0.0.rst816 - aco: allow to schedule SALU/SMEM through exec changes
D20.0.0.rst722 - aco: check if SALU instructions are predeceeded by exec when
D20.2.0.rst3931 - aco: optimize swizzled SALU 8/16-bit conversions
D21.2.0.rst5009 - aco: Eliminate SALU comparison when SCC can be used instead.