Searched refs:SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT (Results 1 – 6 of 6) sorted by relevance
378 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in brw_instruction_name()1137 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in has_side_effects()
502 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT, enumerator
866 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) in generate_urb_write()870 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) in generate_urb_write()2422 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in generate_code()
926 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in instruction_desc()
230 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in is_send_from_grf()305 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in is_payload()981 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in size_read()1631 prev->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) { in emit_gs_thread_end()7576 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in get_lowered_simd_width()
2291 opcode = SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT; in emit_gs_control_data_bits()3060 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT : in nir_emit_tcs_intrinsic()