Searched refs:SI_CONTEXT_INV_L2 (Results 1 – 7 of 7) sorted by relevance
59 wait_flags |= wait_ps_cs | SI_CONTEXT_INV_L2; in si_flush_gfx_cs()379 SI_CONTEXT_INV_L2 | SI_CONTEXT_START_PIPELINE_STATS; in si_begin_new_gfx_cs()607 SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_L2_METADATA | in gfx10_emit_cache_flush()647 if (flags & SI_CONTEXT_INV_L2) { in gfx10_emit_cache_flush()801 SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_L2_METADATA | in si_emit_cache_flush()936 if (flags & SI_CONTEXT_INV_L2) { in si_emit_cache_flush()941 flags &= ~(SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_VCACHE); in si_emit_cache_flush()975 if (flags & SI_CONTEXT_INV_L2 || (sctx->chip_class <= GFX7 && (flags & SI_CONTEXT_WB_L2))) { in si_emit_cache_flush()
84 #define SI_CONTEXT_INV_L2 (1 << 6) macro1744 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_CB_shader_coherent()1753 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_CB_shader_coherent()1758 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_CB_shader_coherent()1769 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_DB_shader_coherent()1778 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_DB_shader_coherent()1783 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_DB_shader_coherent()
399 SI_CONTEXT_INV_L2 | SI_CONTEXT_PFP_SYNC_ME; in si_thread_trace_start()442 SI_CONTEXT_INV_L2 | SI_CONTEXT_PFP_SYNC_ME; in si_thread_trace_stop()865 if (flags & SI_CONTEXT_INV_L2) in si_sqtt_describe_barrier_end()
237 (cache_policy == L2_LRU ? 0 : SI_CONTEXT_INV_L2) | in si_test_dma_perf()
54 (cache_policy == L2_BYPASS ? SI_CONTEXT_INV_L2 : 0); in si_get_flush_flags()
75 sctx->flags |= SI_CONTEXT_INV_L2; in si_execute_clears()
1340 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2; in radeonsi_screen_create_impl()