Searched refs:SI_SGPR_VS_VB_DESCRIPTOR_FIRST (Results 1 – 5 of 5) sorted by relevance
225 SI_SGPR_VS_VB_DESCRIPTOR_FIRST = 12, enumerator
286 assert(user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST); in declare_vb_descriptor_input_sgprs()289 for (unsigned i = user_sgprs; i < SI_SGPR_VS_VB_DESCRIPTOR_FIRST; i++) in declare_vb_descriptor_input_sgprs()573 assert(num_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST); in si_init_shader_args()575 SI_SGPR_VS_VB_DESCRIPTOR_FIRST + shader->selector->num_vbos_in_user_sgprs * 4; in si_init_shader_args()
1226 8 + SI_SGPR_VS_VB_DESCRIPTOR_FIRST + i * 4); in gfx10_emit_ngg_culling_epilogue()1237 vgpr = 8 + SI_SGPR_VS_VB_DESCRIPTOR_FIRST + shader->selector->num_vbos_in_user_sgprs * 4; in gfx10_emit_ngg_culling_epilogue()
1815 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, num_vb_sgprs); in si_upload_and_prefetch_VB_descriptors()1899 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, num_sgprs); in si_upload_and_prefetch_VB_descriptors()
486 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1); in si_get_num_vs_user_sgprs()489 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4; in si_get_num_vs_user_sgprs()