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Searched refs:SLOT1 (Results 1 – 12 of 12) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepIICHVX.td106 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
110 InstrItinData <tc_05058f6f, /*SLOT1,LOAD,VA_DV*/
111 [InstrStage<1, [SLOT1], 0>,
116 InstrItinData <tc_05ac6f98, /*SLOT1,LOAD,VA*/
117 [InstrStage<1, [SLOT1], 0>,
123 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
138 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
144 InstrStage<1, [SLOT1], 0>,
150 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
161 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
[all …]
DHexagonDepIICScalar.td186 InstrItinData <tc_0371abea, [InstrStage<1, [SLOT0, SLOT1]>]>,
187 InstrItinData <tc_05c070ec, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
191 InstrItinData <tc_0a705168, [InstrStage<1, [SLOT0, SLOT1]>]>,
193 InstrItinData <tc_0b2be201, [InstrStage<1, [SLOT0, SLOT1]>]>,
196 InstrItinData <tc_14b272fa, [InstrStage<1, [SLOT0, SLOT1]>]>,
198 InstrItinData <tc_15aa71c5, [InstrStage<1, [SLOT0, SLOT1]>]>,
200 InstrItinData <tc_17e0d2cd, [InstrStage<1, [SLOT0, SLOT1]>]>,
203 InstrItinData <tc_1ae57e39, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
204 InstrItinData <tc_1b6f7cec, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
206 InstrItinData <tc_1c80410a, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
[all …]
DHexagonScheduleV55.td12 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
24 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>,
25 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
34 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonScheduleV5.td14 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
24 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>,
25 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>
32 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonIICScalar.td15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
26 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
28 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
DHexagonIICHVX.td15 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
22 // thus changing 'MaxResTerms' to 5. Instead, both SLOT0 and SLOT1 are
26 InstrStage<1, [SLOT1], 0>,
DHexagonScheduleV60.td18 // | SLOT1 | LD ST ALU32 |
64 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV62.td20 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV65.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV66.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonSchedule.td14 def SLOT1 : FuncUnit;
/third_party/python/Objects/
Dtypeobject.c7054 #define SLOT1(FUNCNAME, OPSTR, ARG1TYPE) \ macro
7250 SLOT1(slot_mp_subscript, "__getitem__", PyObject *)
7380 SLOT1(slot_nb_inplace_add, "__iadd__", PyObject *)
7381 SLOT1(slot_nb_inplace_subtract, "__isub__", PyObject *)
7382 SLOT1(slot_nb_inplace_multiply, "__imul__", PyObject *)
7383 SLOT1(slot_nb_inplace_matrix_multiply, "__imatmul__", PyObject *)
7384 SLOT1(slot_nb_inplace_remainder, "__imod__", PyObject *)
7393 SLOT1(slot_nb_inplace_lshift, "__ilshift__", PyObject *)
7394 SLOT1(slot_nb_inplace_rshift, "__irshift__", PyObject *)
7395 SLOT1(slot_nb_inplace_and, "__iand__", PyObject *)
[all …]