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Searched refs:SMULL (Results 1 – 20 of 20) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenMCPseudoLowering.inc156 TmpInst.setOpcode(ARM::SMULL);
DARMGenAsmWriter.inc2447 3223272U, // SMULL
6671 33554432U, // SMULL
11447 case ARM::SMULL:
11553 case ARM::SMULL:
DARMGenSubtargetInfo.inc5213 { 1, 10, 11, 543, 546 }, // 381 SMULL
6260 { 1, 63, 65, 2322, 2326 }, // 381 SMULL
7307 { 1, 283, 284, 5321, 5325 }, // 381 SMULL
11129 {DBGFIELD("SMULL") 1, false, false, 15, 2, 15, 2, 0, 0}, // #381
12578 {DBGFIELD("SMULL") 2, false, false, 98, 1, 49, 2, 64, 2}, // #381
14027 {DBGFIELD("SMULL") 2, false, false, 13, 1, 7, 2, 64, 2}, // #381
15476 {DBGFIELD("SMULL") 1, false, false, 111, 1, 9, 1, 64, 3}, // #381
16925 {DBGFIELD("SMULL") 3, false, false, 173, 2, 57, 2, 0, 0}, // #381
DARMGenMCCodeEmitter.inc1755 UINT64_C(12583056), // SMULL
15170 case ARM::SMULL:
18430 CEFBS_IsARM_HasV6, // SMULL = 1742
DARMGenAsmMatcher.inc11165 …{ 1307 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AM…
11166 …{ 1307 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AM…
DARMGenInstrInfo.inc1757 SMULL = 1742,
4631 SMULL = 381,
7588 …::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1742 = SMULL
DARMGenDisassemblerTables.inc128 /* 307 */ MCD::OPC_Decode, 206, 13, 6, // Opcode: SMULL
DARMGenDAGISel.inc48036 /*104233*/ OPC_MorphNodeTo2, TARGET_VAL(ARM::SMULL), 0,
48039 // Dst: (SMULL:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
/third_party/pcre2/pcre2/src/sljit/
DsljitNativeARM_32.c108 #define SMULL 0xe0c00090 macro
1232 …FAIL_IF(push_inst(compiler, SMULL | (reg_map[TMP_REG1] << 16) | (reg_map[dst] << 12) | (reg_map[sr… in emit_single_op()
1710 return push_inst(compiler, (op == SLJIT_LMUL_UW ? UMULL : SMULL) in sljit_emit_op0()
DsljitNativeARM_T2_32.c164 #define SMULL 0xfb800000 macro
835 FAIL_IF(push_inst32(compiler, SMULL | RT4(dst) | RD4(TMP_REG2) | RN4(arg1) | RM4(arg2))); in emit_op_imm()
1268 return push_inst32(compiler, (op == SLJIT_LMUL_UW ? UMULL : SMULL) in sljit_emit_op0()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h195 SMULL, enumerator
DAArch64InstrInfo.td523 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
4494 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
4521 // Additional patterns for SMULL and UMULL
5632 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
DAArch64ISelLowering.cpp1369 case AArch64ISD::SMULL: return "AArch64ISD::SMULL"; in getTargetNodeName()
2886 NewOpc = AArch64ISD::SMULL; in LowerMUL()
2896 NewOpc = AArch64ISD::SMULL; in LowerMUL()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleR52.td278 "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$",
DARMScheduleSwift.td281 (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>;
DARMScheduleA57.td298 // Multiply long: SMULL, UMULL
DARMInstrInfo.td4162 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4184 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
6178 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6195 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
DARMScheduleA9.td2551 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenFastISel.inc5633 // FastEmit functions for AArch64ISD::SMULL.
9797 …case AArch64ISD::SMULL: return fastEmit_AArch64ISD_SMULL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsK…
DAArch64GenAsmWriter.inc13876 // FMUL_ZZZI_D, FMUL_ZZZI_S, MUL_ZZZI_D, MUL_ZZZI_S, SMULLB_ZZZI_D, SMULL...