Searched refs:SMULO (Results 1 – 16 of 16) sorted by relevance
258 SMULO, UMULO, enumerator
325 case Intrinsic::smul_with_overflow: Opcode = ISD::SMULO; break; in mightUseCTR()
452 case ISD::SMULO: in LegalizeOp()943 case ISD::SMULO: in Expand()
296 case ISD::SMULO: return "smulo"; in getOperationName()
145 case ISD::SMULO: in PromoteIntegerResult()1139 if (N->getOpcode() == ISD::SMULO) { in PromoteIntRes_XMULO()1904 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; in ExpandIntegerResult()3040 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO; in ExpandIntRes_MULFIX()
161 case ISD::SMULO: in ScalarizeVectorResult()956 case ISD::SMULO: in SplitVectorResult()2767 case ISD::SMULO: in WidenVectorResult()
7197 } else if (Signed && isOperationLegalOrCustom(ISD::SMULO, VT)) { in expandFixedPointMul()7199 DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); in expandFixedPointMul()7468 bool isSigned = Node->getOpcode() == ISD::SMULO; in expandMULO()
2845 case ISD::SMULO: in computeKnownBits()3735 case ISD::SMULO: in ComputeNumSignBits()9330 Opcode == ISD::UMULO || Opcode == ISD::SMULO) && in UnrollVectorOverflowOp()
3499 case ISD::SMULO: { in ExpandNode()
1530 case ISD::SMULO: in visit()4292 bool IsSigned = (ISD::SMULO == N->getOpcode()); in visitMULO()
6641 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; in visitIntrinsicCall()
1675 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()2936 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()2938 bool isSigned = (opcode == ISD::SMULO); in LowerUMULO_SMULO()3057 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); in LowerOperation()
669 setOperationAction(ISD::SMULO, VT, Expand); in initActions()
381 setOperationAction(ISD::SMULO, MVT::i32, Custom); in AArch64TargetLowering()382 setOperationAction(ISD::SMULO, MVT::i64, Custom); in AArch64TargetLowering()2234 case ISD::SMULO: in getAArch64XALUOOp()2237 bool IsSigned = Op.getOpcode() == ISD::SMULO; in getAArch64XALUOOp()2340 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)); in isOverflowIntrOpRes()3193 case ISD::SMULO: in LowerOperation()
4447 case ISD::SMULO: in getARMXALUOOp()5218 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBRCOND()5269 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBR_CC()
1931 setOperationAction(ISD::SMULO, VT, Custom); in X86TargetLowering()21988 case ISD::SMULO: in getX86XALUOOp()22278 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT()22833 Cond.getOperand(0).getOpcode() == ISD::SMULO || in LowerBRCOND()22886 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerBRCOND()28635 case ISD::SMULO: in LowerOperation()