| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 37 SRA = 0x37, enumerator
96 case SRA: in lanaiAluCodeToString()
114 .Case("sha", SRA) in stringToLanaiAluCode()
138 case ISD::SRA: in isdToLanaiAluCode()
139 return AluCode::SRA; in isdToLanaiAluCode()
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| D | LanaiMemAluCombiner.cpp | 224 return LPAC::SRA; in mergedAluCode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
304 { ISD::SRA, MVT::v2i64, 1 }, in getArithmeticInstrCost()
305 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
306 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
319 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
321 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
334 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
338 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. in getArithmeticInstrCost()
453 { ISD::SRA, MVT::v16i16, 1 }, // psraw. in getArithmeticInstrCost()
474 { ISD::SRA, MVT::v8i16, 1 }, // psraw. in getArithmeticInstrCost()
[all …]
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeSPARC_32.c | 60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst)); in emit_single_op()
71 …return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)… in emit_single_op()
114 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(dst) | IMM(31), DR(TMP_REG1))); in emit_single_op()
136 FAIL_IF(push_inst(compiler, SRA | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
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| D | sljitNativeMIPS_32.c | 93 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(24), DR(dst)); in emit_single_op()
112 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(16), DR(dst)); in emit_single_op()
387 FAIL_IF(push_inst(compiler, SRA | T(dst) | DA(OTHER_FLAG) | SH_IMM(31), OTHER_FLAG)); in emit_single_op()
411 EMIT_SHIFT(SRA, SRAV); in emit_single_op()
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| D | sljitNativeMIPS_64.c | 483 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRA32, SRA) | T(dst) | DA(OTHER_FLAG) | SH_IMM(31), OTHER_F… in emit_single_op()
507 EMIT_SHIFT(DSRA, DSRA32, SRA, DSRAV, SRAV); in emit_single_op()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
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| D | ARMISelLowering.cpp | 192 setOperationAction(ISD::SRA, VT, Custom); in addTypeForNEON()
263 setOperationAction(ISD::SRA, VT, Custom); in addMVEVectorTypes()
920 setTargetDAGCombine(ISD::SRA); in ARMTargetLowering()
1073 setOperationAction(ISD::SRA, MVT::i64, Custom); in ARMTargetLowering()
1806 if (Op.getOpcode() != ISD::SRA) in isSRA16()
3672 SDValue SRA = in LowerINTRINSIC_WO_CHAIN() local
3673 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy)); in LowerINTRINSIC_WO_CHAIN()
3674 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand); in LowerINTRINSIC_WO_CHAIN()
3695 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31); in LowerINTRINSIC_WO_CHAIN()
4455 DAG.getNode(ISD::SRA, dl, Op.getValueType(), in getARMXALUOOp()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 174 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence() local
176 return SRA; in addIPMSequence()
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| D | SystemZShortenInst.cpp | 327 TwoOperandOpcode == SystemZ::SRA) { in processBlock()
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| D | SystemZISelDAGToDAG.cpp | 907 case ISD::SRA: { in expandRxSBG()
917 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) { in expandRxSBG()
1859 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean()
1878 Result = CurDAG->getNode(ISD::SRA, DL, VT, Result, in expandSelectBoolean()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 89 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
696 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSAT()
776 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
990 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRA()
1291 case ISD::SRA: in PromoteIntegerOperand()
1896 case ISD::SRA: in ExpandIntegerResult()
2013 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
2015 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
2018 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
2020 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
[all …]
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| D | LegalizeVectorOps.cpp | 386 case ISD::SRA: in LegalizeOp()
819 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt); in ExpandLoad()
1057 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || in ExpandSEXTINREG()
1069 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); in ExpandSEXTINREG()
1126 return DAG.getNode(ISD::SRA, DL, VT, in ExpandSIGN_EXTEND_VECTOR_INREG()
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| D | DAGCombiner.cpp | 1269 if (Opc == ISD::SRA) in PromoteIntShiftOp()
1540 case ISD::SRA: return visitSRA(N); in visit()
1662 case ISD::SRA: in combine()
2073 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL; in foldAddSubOfSignBit()
2995 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
2998 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
3210 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) { in visitSUB()
3254 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt); in visitSUB() local
3255 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA); in visitSUB()
3835 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0, in visitSDIVLike()
[all …]
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| /third_party/icu/icu4c/source/data/region/ |
| D | pl.txt | 137 HK{"SRA Hongkong (Chiny)"}
191 MO{"SRA Makau (Chiny)"}
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 76 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
79 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
344 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
985 case ISD::SRA: in LowerShifts()
989 Victim = (Opc == ISD::SRA) in LowerShifts()
1207 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 245 case LPAC::SRA: in getRrMemoryOpValue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 837 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; in LowerSRXParts() local
852 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
856 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
857 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; in LowerSRXParts()
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| D | AMDGPUISelLowering.cpp | 371 setOperationAction(ISD::SRA, VT, Expand); in AMDGPUTargetLowering()
488 setTargetDAGCombine(ISD::SRA); in AMDGPUTargetLowering()
1559 jq = DAG.getNode(ISD::SRA, DL, VT, jq, in LowerDIVREM24()
2110 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
2219 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp); in LowerFROUND64()
2220 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64, in LowerFROUND64()
2424 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit); in LowerINT_TO_FP32()
3129 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3139 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3251 Src.getOpcode() == ISD::SRA || in performTruncateCombine()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 81 setOperationAction(ISD::SRA, MVT::i8, Custom); in AVRTargetLowering()
84 setOperationAction(ISD::SRA, MVT::i16, Custom); in AVRTargetLowering()
303 case ISD::SRA: in LowerShifts()
313 case ISD::SRA: in LowerShifts()
688 case ISD::SRA: in LowerOperation()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 102 setOperationAction(ISD::SRA, MVT::i32, Legal); in ARCTargetLowering()
192 SDValue SR = DAG.getNode(ISD::SRA, dl, MVT::i32, LS, in LowerSIGN_EXTEND_INREG()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 186 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest) in expandAtomicCmpSwapSubword()
561 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest) in expandAtomicBinOpSubword()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 403 case ISD::SRA: in getShiftTypeForNode()
1681 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in isBitfieldExtractOpFromSExtInReg()
1744 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && in isBitfieldExtractOpFromShr()
1802 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri; in isBitfieldExtractOpFromShr()
1804 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri; in isBitfieldExtractOpFromShr()
1818 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in tryBitfieldExtractOpFromSExt()
1877 case ISD::SRA: in isBitfieldExtractOp()
2571 case ISD::SRA: in tryShiftAmountMod()
3075 case ISD::SRA: in Select()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 107 setOperationAction(ISD::SRA, T, Custom); in initializeHVXLowering()
159 setOperationAction(ISD::SRA, T, Custom); in initializeHVXLowering()
1548 case ISD::SRA: in LowerHvxOperation()
1574 case ISD::SRA: in LowerHvxOperation()
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