| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.td | 64 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, R8, SpLim
68 // Pass in STG registers: F1, ..., F6
71 // Pass in STG registers: D1, ..., D6
74 // Pass in STG registers: XMM1, ..., XMM6
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| D | SystemZInstrInfo.cpp | 1099 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD; in foldMemoryOperandImpl()
1232 splitMove(MI, SystemZ::STG); in expandPostRAPseudo()
1481 StoreOpcode = SystemZ::STG; in getLoadStoreOpcodes()
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| D | SystemZFrameLowering.cpp | 517 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG)) in emitPrologue()
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| D | SystemZScheduleZ196.td | 192 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
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| D | SystemZScheduleZEC12.td | 200 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
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| D | SystemZScheduleZ13.td | 220 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
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| D | SystemZScheduleZ14.td | 221 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
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| D | SystemZScheduleZ15.td | 222 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
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| D | SystemZISelLowering.cpp | 7796 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false); in EmitInstrWithCustomInserter()
7798 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true); in EmitInstrWithCustomInserter()
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| D | SystemZInstrInfo.td | 448 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
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| /third_party/libphonenumber/resources/carrier/en/ |
| D | 252.txt | 37 2529|STG
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SelectionDAGInfo.cpp | 78 const unsigned OpCode1 = ZeroData ? AArch64ISD::STZG : AArch64ISD::STG; in EmitUnrolledSetTag()
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| D | AArch64CallingConvention.td | 330 // which defines the registers for the Spineless Tagless G-Machine (STG) that
331 // GHC uses to implement lazy evaluation. The generic STG machine has a set of
335 // The STG Machine is documented here:
357 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
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| D | AArch64ISelLowering.h | 273 STG, enumerator
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| D | AArch64InstrInfo.td | 539 def AArch64stg : SDNode<"AArch64ISD::STG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemO…
1511 defm STG : MemTagStore<0b00, "stg">;
1548 // Large STG to be expanded into a loop. $Rm is the size, $Rn is start address.
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| D | AArch64ISelLowering.cpp | 1375 case AArch64ISD::STG: return "AArch64ISD::STG"; in getTargetNodeName()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallingConv.td | 676 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
680 // Pass in STG registers: F1, F2, F3, F4, D1, D2
961 // Pass in STG registers: Base, Sp, Hp, R1
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.td | 121 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
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| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3.h | 2152 INSTR4NODST(STG)
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| /third_party/eudev/hwdb/ |
| D | 20-acpi-vendor.hwdb | 6354 acpi:STG*:
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| D | 20-pci-vendor-model.hwdb | 17550 ID_MODEL_FROM_DATABASE=STG 2000X
17553 ID_MODEL_FROM_DATABASE=STG 1764X
17622 ID_MODEL_FROM_DATABASE=STG 1764X
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.0.0.rst | 2000 - freedreno/a6xx: Add register offset for STG/LDG
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| D | 20.1.0.rst | 1674 - freedreno/ir3: Fix the disasm of half-float STG dests.
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