/third_party/optimized-routines/ |
D | Makefile | 13 SUBS = math string networking macro 33 $(foreach sub,$(SUBS),$(eval include $(srcdir)/$(sub)/Dir.mk)) 45 all: $(SUBS:%=all-%) 47 ALL_FILES = $(foreach sub,$(SUBS),$($(sub)-files)) 67 clean: $(SUBS:%=clean-%) 85 install: $(SUBS:%=install-%) 87 check: $(SUBS:%=check-%)
|
D | config.mk.dist | 7 SUBS = math string networking
|
/third_party/cmsis/CMSIS/DSP/Source/TransformFunctions/ |
D | arm_bitreversal2.S | 111 SUBS r3,r3,#1 134 SUBS r3,r3,#1 176 SUBS r3,r3,#1 208 SUBS r3,r3,#1
|
/third_party/e2fsprogs/ |
D | Makefile.in | 30 SUBS= util/subst.conf lib/config.h $(top_builddir)/lib/dirpaths.h \ 45 @for i in $(SUBS) ; do if test -d `dirname $$i` ; \ 132 $(RM) -f $(SUBS) 161 $(RM) -f $(SUBS) $(SUBST_CONF) \
|
/third_party/skia/third_party/externals/freetype/src/autofit/ |
D | afstyles.h | 72 STYLE_LATIN( s, S, subs, SUBS, ds, \
|
/third_party/freetype/src/autofit/ |
D | afstyles.h | 72 STYLE_LATIN( s, S, subs, SUBS, ds, \
|
/third_party/flutter/skia/third_party/externals/freetype/src/autofit/ |
D | afstyles.h | 72 STYLE_LATIN( s, S, subs, SUBS, ds, \
|
/third_party/pcre2/pcre2/src/sljit/ |
D | sljitNativeARM_64.c | 130 #define SUBS 0xeb000000 macro 813 return push_inst(compiler, SUBS | RD(TMP_ZERO) | RN(TMP_LR) | RM(dst) | (2 << 22) | (63 << 10)); in emit_op_imm() 817 return push_inst(compiler, SUBS | RD(TMP_ZERO) | RN(TMP_LR) | RM(dst) | (2 << 22) | (63 << 10)); in emit_op_imm() 843 return push_inst(compiler, (SUBS ^ inv_bits) | RD(TMP_ZERO) | RN(dst) | RM(TMP_ZERO)); in emit_op_imm()
|
D | sljitNativeARM_T2_32.c | 166 #define SUBS 0x1a00 macro 824 return push_inst16(compiler, SUBS | RD3(dst) | RN3(arg1) | RM3(arg2)); in emit_op_imm()
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMISelLowering.h | 93 SUBS, // Flag-setting subtraction. enumerator
|
D | ARMInstrInfo.td | 166 def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>; 3666 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3671 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3676 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>;
|
D | ARMISelLowering.cpp | 1570 case ARMISD::SUBS: return "ARMISD::SUBS"; in getTargetNodeName() 14543 DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS); in PerformCMOVCombine() 14557 DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS); in PerformCMOVCombine() 14582 ((FalseVal.getOpcode() == ARMISD::SUBS && in PerformCMOVCombine()
|
D | ARMInstrThumb2.td | 4066 // B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction. 4095 // B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.h | 57 SUBS, enumerator
|
D | AArch64SchedKryoDetails.td | 2189 (instregex "SUBS?(W|X)ri")>; 2195 (instregex "SUBS?(W|X)rx")>; 2201 (instregex "SUBS?(W|X)rs")>; 2207 (instregex "SUBS?(W|X)rr")>;
|
D | AArch64SchedThunderX2T99.td | 429 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", 451 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", 470 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
|
D | AArch64ISelLowering.cpp | 1252 case AArch64ISD::SUBS: return "AArch64ISD::SUBS"; in getTargetNodeName() 1726 unsigned Opcode = AArch64ISD::SUBS; in emitComparison() 2226 Opc = AArch64ISD::SUBS; in getAArch64XALUOOp() 2230 Opc = AArch64ISD::SUBS; in getAArch64XALUOOp() 2268 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits) in getAArch64XALUOOp() 2280 DAG.getNode(AArch64ISD::SUBS, DL, VTs, in getAArch64XALUOOp() 2296 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits) in getAArch64XALUOOp() 2302 DAG.getNode(AArch64ISD::SUBS, DL, VTs, in getAArch64XALUOOp() 2441 Opc = AArch64ISD::SUBS; in LowerADDC_ADDE_SUBC_SUBE() 9670 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32), in performIntegerAbsCombine() [all …]
|
D | AArch64InstrInfo.td | 410 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>; 1217 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">; 1219 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
D | ARMGenFastISel.inc | 3090 // FastEmit functions for ARMISD::SUBS. 5480 case ARMISD::SUBS: return fastEmit_ARMISD_SUBS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6577 // FastEmit functions for ARMISD::SUBS. 6692 …case ARMISD::SUBS: return fastEmit_ARMISD_SUBS_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm… 6702 // FastEmit functions for ARMISD::SUBS. 6796 …case ARMISD::SUBS: return fastEmit_ARMISD_SUBS_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1… 6868 // FastEmit functions for ARMISD::SUBS. 6892 …case ARMISD::SUBS: return fastEmit_ARMISD_SUBS_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, im… 6933 // FastEmit functions for ARMISD::SUBS. 7047 …case ARMISD::SUBS: return fastEmit_ARMISD_SUBS_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, i…
|
D | ARMGenDAGISel.inc | 43432 /* 94279*/ /*SwitchOpcode*/ 111|128,1/*239*/, TARGET_VAL(ARMISD::SUBS),// ->94522
|