Home
last modified time | relevance | path

Searched refs:SchedModel (Results 1 – 25 of 89) sorted by relevance

1234

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetSchedule.cpp40 return EnableSchedModel && SchedModel.hasInstrSchedModel(); in hasInstrSchedModel()
65 SchedModel = TSInfo->getSchedModel(); in init()
69 unsigned NumRes = SchedModel.getNumProcResourceKinds(); in init()
71 ResourceLCM = SchedModel.IssueWidth; in init()
73 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits; in init()
77 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; in init()
79 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits; in init()
136 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
147 SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
189 return TII->defaultDefLatency(SchedModel, *DefMI); in computeOperandLatency()
[all …]
DMachineScheduler.cpp1177 if (SchedModel.mustBeginGroup(SU.getInstr()) && in dump()
1178 SchedModel.mustEndGroup(SU.getInstr())) in dump()
1885 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { in init() argument
1887 if (!SchedModel->hasInstrSchedModel()) in init()
1889 RemainingCounts.resize(SchedModel->getNumProcResourceKinds()); in init()
1892 RemIssueCount += SchedModel->getNumMicroOps(SU.getInstr(), SC) in init()
1893 * SchedModel->getMicroOpFactor(); in init()
1895 PI = SchedModel->getWriteProcResBegin(SC), in init()
1896 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) { in init()
1898 unsigned Factor = SchedModel->getResourceFactor(PIdx); in init()
[all …]
DMachineTraceMetrics.cpp73 SchedModel.init(&ST); in runOnMachineFunction()
76 SchedModel.getNumProcResourceKinds()); in runOnMachineFunction()
109 unsigned PRKinds = SchedModel.getNumProcResourceKinds(); in getResources()
120 if (!SchedModel.hasInstrSchedModel()) in getResources()
122 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI); in getResources()
127 PI = SchedModel.getWriteProcResBegin(SC), in getResources()
128 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) { in getResources()
139 PRCycles[K] * SchedModel.getResourceFactor(K); in getResources()
148 unsigned PRKinds = SchedModel.getNumProcResourceKinds(); in getProcResourceCycles()
160 unsigned PRKinds = MTM.SchedModel.getNumProcResourceKinds(); in Ensemble()
[all …]
DEarlyIfConversion.cpp704 MCSchedModel SchedModel; member in __anon1e64fd320211::EarlyIfConverter
814 unsigned CritLimit = SchedModel.MispredictPenalty/2; in shouldConvertIf()
912 SchedModel = STI.getSchedModel(); in runOnMachineFunction()
941 TargetSchedModel SchedModel; member in __anon1e64fd320411::EarlyIfPredicator
993 unsigned NumCycles = SchedModel.computeInstrLatency(&I, false); in shouldConvertIf()
1007 unsigned NumCycles = SchedModel.computeInstrLatency(&I, false); in shouldConvertIf()
1013 unsigned NumCycles = SchedModel.computeInstrLatency(&I, false); in shouldConvertIf()
1047 SchedModel.init(&STI); in runOnMachineFunction()
DScheduleDAGInstrs.cpp120 SchedModel.init(&ST); in ScheduleDAGInstrs()
270 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
319 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
445 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use, in addVRegDefDeps()
489 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
581 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr()); in initSUnits()
591 if (SchedModel.hasInstrSchedModel()) { in initSUnits()
594 make_range(SchedModel.getWriteProcResBegin(SC), in initSUnits()
595 SchedModel.getWriteProcResEnd(SC))) { in initSUnits()
596 switch (SchedModel.getProcResource(PRE.ProcResourceIdx)->BufferSize) { in initSUnits()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetSchedule.h34 MCSchedModel SchedModel; variable
50 TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {} in TargetSchedModel()
75 const MCSchedModel *getMCSchedModel() const { return &SchedModel; } in getMCSchedModel()
96 unsigned getProcessorID() const { return SchedModel.getProcessorID(); } in getProcessorID()
99 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth()
114 return SchedModel.getNumProcResourceKinds(); in getNumProcResourceKinds()
119 return SchedModel.getProcResource(PIdx); in getProcResource()
126 return SchedModel.getProcResource(PIdx)->Name; in getResourceName()
161 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; } in getMicroOpBufferSize()
166 return SchedModel.getProcResource(PIdx)->BufferSize; in getResourceBufferSize()
DScheduleDAGInstrs.h125 TargetSchedModel SchedModel; variable
262 const TargetSchedModel *getSchedModel() const { return &SchedModel; } in getSchedModel()
266 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) in getSchedClass()
267 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
DMachineScheduler.h598 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
614 const TargetSchedModel *SchedModel = nullptr; variable
727 return RetiredMOps * SchedModel->getMicroOpFactor(); in getCriticalCount()
735 return std::max(CurrCycle * SchedModel->getLatencyFactor(), in getExecutedCount()
889 const TargetSchedModel *SchedModel);
894 const TargetSchedModel *SchedModel = nullptr; variable
DMachineTraceMetrics.h93 TargetSchedModel SchedModel; variable
416 unsigned Factor = SchedModel.getLatencyFactor(); in getCycles()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.cpp152 for (unsigned i = 0; i < SchedModel->getNumProcResourceKinds(); ++i) in nextGroup()
176 PI = SchedModel->getWriteProcResBegin(SC), in dumpSU()
177 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) { in dumpSU()
179 *SchedModel->getProcResource(PI->ProcResourceIdx); in dumpSU()
226 for (unsigned i = 0; i < SchedModel->getNumProcResourceKinds(); ++i) in dumpProcResourceCounters()
236 for (unsigned i = 0; i < SchedModel->getNumProcResourceKinds(); ++i) in dumpProcResourceCounters()
238 dbgs() << SchedModel->getProcResource(i)->Name in dumpProcResourceCounters()
244 << SchedModel->getProcResource(CriticalResourceIdx)->Name in dumpProcResourceCounters()
260 ProcResourceCounters.assign(SchedModel->getNumProcResourceKinds(), 0); in clearProcResCounters()
297 PI = SchedModel->getWriteProcResBegin(SC), in EmitInstruction()
[all …]
DSystemZHazardRecognizer.h48 const TargetSchedModel *SchedModel; variable
112 : TII(tii), SchedModel(SM) { in SystemZHazardRecognizer()
122 if (!SU->SchedClass && SchedModel->hasInstrSchedModel()) in getSchedClass()
123 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr()); in getSchedClass()
DSystemZMachineScheduler.cpp87 HazardRec = SchedStates[MBB] = new SystemZHazardRecognizer(TII, &SchedModel); in enterMBB()
135 SchedModel.init(ST); in SystemZPostRASchedStrategy()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.h41 const TargetSchedModel *SchedModel; variable
52 : SchedModel(SM) { in VLIWResourceModel()
59 Packet.resize(SchedModel->getIssueWidth()); in VLIWResourceModel()
135 const TargetSchedModel *SchedModel = nullptr; member
167 SchedModel = smodel; in init()
175 CriticalPathLength = DAG->getBBSize() / SchedModel->getIssueWidth(); in init()
218 const TargetSchedModel *SchedModel = nullptr; variable
DHexagonMachineScheduler.cpp150 Packet.size() >= SchedModel->getIssueWidth()) { in reserveResources()
255 SchedModel = DAG->getSchedModel(); in initialize()
257 Top.init(DAG, SchedModel); in initialize()
258 Bot.init(DAG, SchedModel); in initialize()
340 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
341 if (IssueCount + uops > SchedModel->getIssueWidth()) in checkHazard()
363 unsigned Width = SchedModel->getIssueWidth(); in bumpCycle()
407 IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); in bumpNode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64StorePairSuppress.cpp34 TargetSchedModel SchedModel; member in __anon229567110111::AArch64StorePairSuppress
87 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldAddSTPToBlock()
129 SchedModel.init(&ST); in runOnMachineFunction()
135 if (!SchedModel.hasInstrSchedModel()) { in runOnMachineFunction()
DAArch64SIMDInstrOpt.cpp71 TargetSchedModel SchedModel; member
222 std::string Subtarget = SchedModel.getSubtargetInfo()->getCPU(); in shouldReplaceInst()
229 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldReplaceInst()
241 SCDescRepl = SchedModel.getMCSchedModel()->getSchedClassDesc( in shouldReplaceInst()
253 ReplCost += SchedModel.computeInstrLatency(IDesc->getOpcode()); in shouldReplaceInst()
255 if (SchedModel.computeInstrLatency(InstDesc->getOpcode()) > ReplCost) in shouldReplaceInst()
291 std::string Subtarget = SchedModel.getSubtargetInfo()->getCPU(); in shouldExitEarly()
702 SchedModel.init(&ST); in runOnMachineFunction()
703 if (!SchedModel.hasInstrSchedModel()) in runOnMachineFunction()
DAArch64SchedKryo.td39 let SchedModel = KryoModel in {
58 let SchedModel = KryoModel in {
137 } // SchedModel = KryoModel
DAArch64Schedule.td10 // const MachineInstr *MI and const TargetSchedModel *SchedModel
14 static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo());
DAArch64SchedFalkor.td35 let SchedModel = FalkorModel in {
66 let SchedModel = FalkorModel in {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSISchedule.td15 static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
158 let SchedModel = SIFullSpeedModel in {
169 } // End SchedModel = SIFullSpeedModel
171 let SchedModel = SIQuarterSpeedModel in {
182 } // End SchedModel = SIQuarterSpeedModel
184 let SchedModel = GFX10SpeedModel in {
206 } // End SchedModel = GFX10SpeedModel
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSchedule.td182 // SchedModel ties these units to a processor for any stand-alone defs
189 SchedMachineModel SchedModel = ?;
204 SchedMachineModel SchedModel = ?;
242 // SchedModel silences warnings but is ignored.
246 SchedMachineModel SchedModel = ?;
251 // SchedModel ties these resources to a processor.
265 SchedMachineModel SchedModel = ?;
307 // type at the same time. This class is unaware of its SchedModel so
314 // SchedModel ties these resources to a processor.
321 SchedMachineModel SchedModel = ?;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenSubtargetInfo.inc19360 …nsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
19386 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel
19389 static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo());
19394 if (SchedModel->getProcessorID() == 2) { // CortexA53Model
19399 if (SchedModel->getProcessorID() == 9) { // ThunderXT8XModel
19406 if (SchedModel->getProcessorID() == 2) { // CortexA53Model
19411 if (SchedModel->getProcessorID() == 9) { // ThunderXT8XModel
19418 if (SchedModel->getProcessorID() == 4) { // ExynosM3Model
19429 if (SchedModel->getProcessorID() == 5) { // ExynosM4Model
19440 if (SchedModel->getProcessorID() == 6) { // ExynosM5Model
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCInstrItineraries.h108 MCSchedModel SchedModel =
119 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F), in InstrItineraryData()
120 Itineraries(SchedModel.InstrItineraries) {} in InstrItineraryData()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCSubtargetInfo.cpp304 assert(CPUEntry->SchedModel && "Missing processor SchedModel value"); in getSchedModelForCPU()
305 return *CPUEntry->SchedModel; in getSchedModelForCPU()
310 const MCSchedModel &SchedModel = getSchedModelForCPU(CPU); in getInstrItineraryForCPU() local
311 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths); in getInstrItineraryForCPU()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenSubtargetInfo.inc19558 …nsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
19587 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel
19590 static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
19593 static_cast<const ARMSubtarget*>(SchedModel->getSubtargetInfo());
19598 if (SchedModel->getProcessorID() == 4) { // CortexA57Model
19603 if (SchedModel->getProcessorID() == 7) { // SwiftModel
19610 if (SchedModel->getProcessorID() == 4) { // CortexA57Model
19615 if (SchedModel->getProcessorID() == 7) { // SwiftModel
19622 if (SchedModel->getProcessorID() == 2) { // CortexA9Model
19644 if (SchedModel->getProcessorID() == 7) { // SwiftModel
[all …]

1234