| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
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| D | ARMMCCodeEmitter.cpp | 1260 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue() local
1261 unsigned SBits = getShiftOp(ShOp); in getLdStSORegOpValue()
1298 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue() local
1300 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] in getAddrMode2OffsetOpValue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1989 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, in CreateShiftExtend() argument
1992 Op->ShiftExtend.Type = ShOp; in CreateShiftExtend()
2743 AArch64_AM::ShiftExtendType ShOp = in tryParseOptionalShiftExtend() local
2760 if (ShOp == AArch64_AM::InvalidShiftExtend) in tryParseOptionalShiftExtend()
2769 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
2770 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
2771 ShOp == AArch64_AM::MSL) { in tryParseOptionalShiftExtend()
2780 AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext())); in tryParseOptionalShiftExtend()
2806 ShOp, MCE->getValue(), true, S, E, getContext())); in tryParseOptionalShiftExtend()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2656 ValueType Ty, SDNode ShOp>
2661 (Ty (ShOp (Ty DPR:$Vn),
2668 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2673 (Ty (ShOp (Ty DPR:$Vn),
2704 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2709 (ResTy (ShOp (ResTy QPR:$Vn),
2717 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2722 (ResTy (ShOp (ResTy QPR:$Vn),
2864 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2871 (Ty (ShOp (Ty DPR:$src1),
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 3410 SDValue ShOp = N->getOperand(1); in WidenVecRes_POWI() local
3411 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_POWI()
3417 SDValue ShOp = N->getOperand(1); in WidenVecRes_Shift() local
3419 EVT ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
3421 ShOp = GetWidenedVector(ShOp); in WidenVecRes_Shift()
3422 ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
3428 ShOp = ModifyToType(ShOp, ShWidenVT); in WidenVecRes_Shift()
3430 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_Shift()
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| D | DAGCombiner.cpp | 4494 SDValue ShOp = N0.getOperand(1); in hoistLogicOpWithSameOpcodeHands() local
4495 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
4496 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
4499 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
4502 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
4507 ShOp = N0.getOperand(0); in hoistLogicOpWithSameOpcodeHands()
4508 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
4509 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
4512 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
4515 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1938 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand() local
1941 ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
1944 ShOp = ARM_AM::lsr; in DecodeSORegMemOperand()
1947 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
1950 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
1954 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
1955 ShOp = ARM_AM::rrx; in DecodeSORegMemOperand()
1963 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); in DecodeSORegMemOperand()
1965 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 1229 class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp,
1231 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)),
|