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Searched refs:VOP2 (Results 1 – 17 of 17) sorted by relevance

/third_party/mesa3d/src/amd/compiler/
Daco_opcodes.py73 VOP2 = 1 << 9 variable in Format
669 VOP2 = { variable
745 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, modifiers) in VOP2:
746 opcode(name, gfx7, gfx9, gfx10, Format.VOP2, InstrClass.Valu32, modifiers, modifiers)
751 opcode(name, gfx7, gfx9, gfx10, Format.VOP2, InstrClass.Valu32, True, False)
Daco_validate.cpp122 else if ((uint32_t)base_format & (uint32_t)Format::VOP2) in validate_ir()
123 base_format = Format::VOP2; in validate_ir()
144 check(base_format == Format::VOP2 || base_format == Format::VOP1 || in validate_ir()
151 check(base_format == Format::VOP2 || base_format == Format::VOP1 || in validate_ir()
Daco_optimizer.cpp2480 new_instr.reset(create_instruction<VOP2_instruction>(new_op, Format::VOP2, 3, 2)); in combine_add_sub_b2i()
2484 create_instruction<VOP3_instruction>(new_op, asVOP3(Format::VOP2), 3, 2)); in combine_add_sub_b2i()
2977 create_instruction<VOP2_instruction>(aco_opcode::v_cndmask_b32, Format::VOP2, 3, 1)); in combine_and_subbrev()
2981 asVOP3(Format::VOP2), 3, 1)); in combine_and_subbrev()
3322 create_instruction<VOP3_instruction>(mul_instr->opcode, asVOP3(Format::VOP2), 2, 1)); in combine_instruction()
3467 create_instruction<VOP2_instruction>(aco_opcode::v_cndmask_b32, Format::VOP2, 3, 1)}; in combine_instruction()
3937 new_mad.reset(create_instruction<VOP2_instruction>(new_op, Format::VOP2, 3, 1)); in apply_literals()
Daco_ir.h100 VOP2 = 1 << 9, enumerator
290 assert(format == Format::VOP1 || format == Format::VOP2 || format == Format::VOPC); in asSDWA()
1251 constexpr bool isVOP2() const noexcept { return (uint16_t)format & (uint16_t)Format::VOP2; } in isVOP2()
Daco_assembler.cpp275 case Format::VOP2: { in emit_instruction()
Daco_register_allocation.cpp2559 instr->format = Format::VOP2; in register_allocation()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td29 field bit VOP2 = 0;
141 let TSFlags{8} = VOP2;
207 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
DVOP2Instructions.td10 // VOP2 Classes
72 let VOP2 = 1;
458 // VOP2 Instructions
869 //===------------------------------- VOP2 -------------------------------===//
915 //===------------------------- VOP2 (with name) -------------------------===//
1124 // VOP2 no carry-in, carry-out.
1132 // VOP2 carry-in, carry-out.
1526 // are VOP2 on SI and VOP3 on VI.
DSIDefines.h33 VOP2 = 1 << 8, enumerator
DSIInstrInfo.h414 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
418 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
DSIInstrInfo.td1440 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1595 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1632 // VOP2 without modifiers
DSIInstructions.td767 // VOP2 Patterns
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2820 SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | in validateConstantBusLimitations()
3260 if ((Desc.TSFlags & (VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA)) == 0) in validateLdsDirect()
6855 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2); in cvtSdwaVOP2()
6859 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true); in cvtSdwaVOP2b()
6863 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true); in cvtSdwaVOP2e()
6895 if (BasicInstType == SIInstrFlags::VOP2 && in cvtSDWA()
6932 case SIInstrFlags::VOP2: in cvtSDWA()
/third_party/mesa3d/docs/relnotes/
D20.3.0.rst1191 - aco: use VOP2 version of v_cvt_pkrtz_f16_f32 on GFX_6_7_10
1192 - aco: use VOP2 for v_cvt_pkrtz_f16_f32 if possible
D20.0.0.rst743 - aco: split read/writelane opcode into VOP2/VOP3 version for SI/CI
D20.1.0.rst1250 - aco: move src1 to vgpr instead of using VOP3 for VOP2 instructions
D20.2.0.rst3873 - aco: use VOP2 version of v_mbcnt_hi_u32_b32 on GFX6/7