Searched refs:VecReg (Results 1 – 6 of 6) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 153 Register VecReg, unsigned LaneIdx,
2902 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt() argument
2919 const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI); in emitExtractVectorElt()
2920 const LLT &VecTy = MRI.getType(VecReg); in emitExtractVectorElt()
2929 Register InsertReg = VecReg; in emitExtractVectorElt()
2935 .addReg(VecReg, 0, ExtractSubReg); in emitExtractVectorElt()
2945 VecTy.getSizeInBits(), &AArch64::FPR128RegClass, VecReg, MIRBuilder); in emitExtractVectorElt()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringX8664.cpp | 4327 Variable *VecReg = nullptr; in lowerMemset() local
4332 auto lowerSet = [this, &Base, SpreadValue, &VecReg](Type Ty, in lowerMemset()
4340 assert(VecReg != nullptr); in lowerMemset()
4341 _storep(VecReg, Mem); in lowerMemset()
4343 assert(VecReg != nullptr); in lowerMemset()
4344 _storeq(VecReg, Mem); in lowerMemset()
4361 VecReg = makeVectorOfZeros(IceType_v16i8); in lowerMemset()
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| D | IceTargetLoweringX8632.cpp | 4906 Variable *VecReg = nullptr; in lowerMemset() local
4911 auto lowerSet = [this, &Base, SpreadValue, &VecReg](Type Ty, in lowerMemset()
4919 assert(VecReg != nullptr); in lowerMemset()
4920 _storep(VecReg, Mem); in lowerMemset()
4922 assert(VecReg != nullptr); in lowerMemset()
4923 _storeq(VecReg, Mem); in lowerMemset()
4940 VecReg = makeVectorOfZeros(IceType_v16i8); in lowerMemset()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 1806 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
1807 LLT VecTy = MRI.getType(VecReg); in widenScalar()
1831 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
1832 LLT VecTy = MRI.getType(VecReg); in widenScalar()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1491 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1494 assert(VecReg == MI.getOperand(1).getReg()); in expandPostRAPseudo()
1498 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
1500 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
1501 .addReg(VecReg, in expandPostRAPseudo()
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| D | SIISelLowering.cpp | 3325 unsigned VecReg, in computeIndirectRegAndOffset() argument
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