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Searched refs:Z6 (Results 1 – 25 of 45) sorted by relevance

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/third_party/openGLES/extensions/ATI/
DATI_separate_stencil.txt163 … STENCIL_BACK_FAIL_ATI Z6 GetIntegerv KEEP 4.1.4 Stencil-buffer
164 … STENCIL_BACK_PASS_DEPTH_FAIL_ATI Z6 GetIntegerv KEEP 4.1.4 Stencil-buffer
165 … STENCIL_BACK_PASS_DEPTH_PASS_ATI Z6 GetIntegerv KEEP 4.1.4 Stencil-buffer
/third_party/skia/third_party/externals/opengl-registry/extensions/ATI/
DATI_separate_stencil.txt163 … STENCIL_BACK_FAIL_ATI Z6 GetIntegerv KEEP 4.1.4 Stencil-buffer
164 … STENCIL_BACK_PASS_DEPTH_FAIL_ATI Z6 GetIntegerv KEEP 4.1.4 Stencil-buffer
165 … STENCIL_BACK_PASS_DEPTH_PASS_ATI Z6 GetIntegerv KEEP 4.1.4 Stencil-buffer
/third_party/openGLES/extensions/EXT/
DEXT_blend_logic_op.txt99 BLEND_EQUATION_EXT GetIntegerv Z6 FUNC_ADD_EXT color-buffer
DEXT_stencil_wrap.txt118 NOTE: the only change is that Z6 type changes to Z8
DEXT_texture_env_combine.txt323 OPERAND0_RGB_EXT GetTexEnviv n x Z6 SRC_COLOR texture
324 OPERAND1_RGB_EXT GetTexEnviv n x Z6 SRC_COLOR texture
DEXT_texenv_op.txt432 TEXTURE_ENV_MODE_ALPHA_EXT Z6 GetTexEnviv MODULATE
433 TEXTURE_ENV_MODE_RGB_EXT Z6 GetTexEnviv MODULATE
439 Z6 ALPHA_OPERAND_A_EXT
DGLX_EXT_visual_info.txt310 GLX_X_VISUAL_TYPE_EXT glXGetConfig Z6
DEXT_light_texture.txt378 TEXTURE_MATERIAL_PARAMETER_EXT GetIntegerv Z6 AMBIENT_AND_DIFFUSE texture
/third_party/skia/third_party/externals/opengl-registry/extensions/EXT/
DEXT_blend_logic_op.txt99 BLEND_EQUATION_EXT GetIntegerv Z6 FUNC_ADD_EXT color-buffer
DEXT_stencil_wrap.txt118 NOTE: the only change is that Z6 type changes to Z8
DEXT_texture_env_combine.txt323 OPERAND0_RGB_EXT GetTexEnviv n x Z6 SRC_COLOR texture
324 OPERAND1_RGB_EXT GetTexEnviv n x Z6 SRC_COLOR texture
DEXT_texenv_op.txt432 TEXTURE_ENV_MODE_ALPHA_EXT Z6 GetTexEnviv MODULATE
433 TEXTURE_ENV_MODE_RGB_EXT Z6 GetTexEnviv MODULATE
439 Z6 ALPHA_OPERAND_A_EXT
DGLX_EXT_visual_info.txt310 GLX_X_VISUAL_TYPE_EXT glXGetConfig Z6
DEXT_light_texture.txt378 TEXTURE_MATERIAL_PARAMETER_EXT GetIntegerv Z6 AMBIENT_AND_DIFFUSE texture
/third_party/openssl/crypto/ec/
Decp_smpl.c958 BIGNUM *rh, *tmp, *Z4, *Z6; in ec_GFp_simple_is_on_curve() local
978 Z6 = BN_CTX_get(ctx); in ec_GFp_simple_is_on_curve()
979 if (Z6 == NULL) in ec_GFp_simple_is_on_curve()
1001 if (!field_mul(group, Z6, Z4, tmp, ctx)) in ec_GFp_simple_is_on_curve()
1024 if (!field_mul(group, tmp, group->b, Z6, ctx)) in ec_GFp_simple_is_on_curve()
/third_party/ffmpeg/libavcodec/aarch64/
Dsimple_idct_neon.S34 #define Z6 8867 //cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 macro
50 .short Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z4c
/third_party/skia/third_party/externals/opengl-registry/extensions/ARB/
DARB_texture_env_combine.txt370 OPERAND0_RGB_ARB GetTexEnviv n x Z6 SRC_COLOR texture
371 OPERAND1_RGB_ARB GetTexEnviv n x Z6 SRC_COLOR texture
/third_party/openGLES/extensions/ARB/
DARB_texture_env_combine.txt380 OPERAND0_RGB_ARB GetTexEnviv n x Z6 SRC_COLOR texture
381 OPERAND1_RGB_ARB GetTexEnviv n x Z6 SRC_COLOR texture
/third_party/skia/third_party/externals/opengl-registry/extensions/INTEL/
DINTEL_texture_scissor.txt205 TEXTURE_SCISSOR_FUNC_INTEL GetIntegerv Z6 GL_GEQUAL, GL_LESS texture / enable
/third_party/openGLES/extensions/INTEL/
DINTEL_texture_scissor.txt205 TEXTURE_SCISSOR_FUNC_INTEL GetIntegerv Z6 GL_GEQUAL, GL_LESS texture / enable
/third_party/mesa3d/src/amd/addrlib/src/gfx10/
Dgfx10SwizzlePattern.h3940 {Y2^X6^Z6, X3^Y5^Z5, Z3^Y4^X5, Y3^X4^Z4, }, // 151
3941 {Y2^X5^Z6, X2^Y5^Z5, Z3^X4^Y4, X3^Y3^Z4, }, // 152
3945 {Y2^X7^Z7, X3^Y6^Z6, Z3^Y5^X6, Y3^X5^Z5, }, // 156
3946 {Y2^X6^Z7, X2^Y6^Z6, Z3^X5^Y5, Y3^X4^Z5, }, // 157
3947 {Y2^X6^Z6, X2^Z5^Y6, Z2^X5^Y5, Y3^X4^Z4, }, // 158
3948 {Y1^X6^Z6, X2^Y5^Z5, Z2^Y4^X5, Y2^X4^Z4, }, // 159
3949 {Y1^X5^Z6, X1^Y5^Z5, Z2^X4^Y4, Y2^X3^Z4, }, // 160
3950 {Y2^X8^Z8, X3^Y7^Z7, Z3^Y6^X7, Y3^X6^Z6, }, // 161
3951 {Y2^X7^Z8, X2^Y7^Z7, Z3^X6^Y6, Y3^X5^Z6, }, // 162
3952 {Y2^X7^Z7, X2^Z6^Y7, Z2^X6^Y6, Y3^X5^Z5, }, // 163
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td79 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,
159 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,
/third_party/mesa3d/src/amd/addrlib/src/core/
Daddrlib2.h200 const UINT_64 Z6 = InitBit(2, 6); variable
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.cpp1205 case AArch64::Z5: Reg = AArch64::Z6; break; in getNextVectorRegister()
1206 case AArch64::Z6: Reg = AArch64::Z7; break; in getNextVectorRegister()
/third_party/curl/src/macos/
Dcurl.mcp.xml.sit.hqx63 eC`jcaFi8Bl$9bp,K,TCp"cJ33fq@Z6`!DldUA,C8J[(2MaI2,p!`$5YT12Mei`2

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