| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredicates.td | 362 // ORR Rd, ZR, Rm, LSL #0
430 [// ORR Rd, ZR, #0
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenDAGISel.inc | 11245 /* 23893*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11251 …// Dst: (MVE_VCMPi8r:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1, ZR:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i…
11258 /* 23923*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11264 …// Dst: (MVE_VCMPi8r:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i…
11271 /* 23953*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11277 …// Dst: (MVE_VCMPs8r:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1, ZR:{ *:[i32] }, 10:{ *:[i32] }, 1:{ *:[…
11284 /* 23983*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11290 …// Dst: (MVE_VCMPs8r:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1, ZR:{ *:[i32] }, 11:{ *:[i32] }, 1:{ *:[…
11297 /* 24013*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11303 …// Dst: (MVE_VCMPs8r:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1, ZR:{ *:[i32] }, 12:{ *:[i32] }, 1:{ *:[…
[all …]
|
| D | ARMGenRegisterInfo.inc | 38 ZR = 18,
1495 { ARM::ZR },
1627 …::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR,
1667 …::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR,
3032 { 15U, ARM::ZR },
3084 { 15U, ARM::ZR },
3124 { ARM::ZR, 15U },
3177 { ARM::ZR, 15U },
5977 …:R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::ZR };
6015 …:R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::ZR };
|
| D | ARMGenAsmWriter.inc | 12434 // (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 188
12436 {AliasPatternCond::K_Reg, ARM::ZR},
12437 {AliasPatternCond::K_Reg, ARM::ZR},
12444 // (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 196
12446 {AliasPatternCond::K_Reg, ARM::ZR},
12447 {AliasPatternCond::K_Reg, ARM::ZR},
|
| D | ARMGenGlobalISel.inc | 32425 …{ *:[v4i32] }:$v1) => (MVE_VCMPi32r:{ *:[v4i1] } MQPR:{ *:[v4i32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[…
32429 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
32463 …{ *:[v8i16] }:$v1) => (MVE_VCMPi32r:{ *:[v8i1] } MQPR:{ *:[v8i16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[…
32467 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
32501 … *:[v16i8] }:$v1) => (MVE_VCMPi32r:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1, ZR:{ *:[i32] }, 1:{ *:[…
32505 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
35549 …{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[…
35553 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
35627 …{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[…
35631 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
[all …]
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| /third_party/boost/libs/wave/test/testwave/testfiles/ |
| D | t_5_035.hpp | 1036 #define ZR macro
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 210 def ZR : ARMReg<15, "zr">, DwarfRegNum<[15]>;
266 def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), ZR)> {
|
| D | ARMInstrMVE.td | 3777 (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc))>;
3779 (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), ZR, fc))>;
3781 (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), ZR, fc))>;
3784 …(v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1)…
3786 …(v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1)…
3788 …(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1)…
3823 (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc))>;
3825 (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc))>;
3828 (v8i1 (MVE_VCMPf32r (v8f16 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>;
3830 (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>;
[all …]
|
| D | ARMBaseRegisterInfo.cpp | 216 markSuperRegs(Reserved, ARM::ZR); in getReservedRegs()
|
| D | ARMInstrThumb2.td | 5427 (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
5430 (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
|
| /third_party/curl/src/macos/ |
| D | curl.mcp.xml.sit.hqx | 57 P"Z19[8kVVN86PN0#LLPpq&`6QI1)ZR-h3b"[H'qCf&q%J1$CRiFD6AhC'iAdA!5
|
| /third_party/flutter/skia/third_party/externals/icu/source/data/curr/ |
| D | supplementalData.txt | 4628 ZR{
|
| /third_party/icu/icu4c/source/data/curr/ |
| D | supplementalData.txt | 4651 ZR{
|
| /third_party/skia/third_party/externals/icu/source/data/curr/ |
| D | supplementalData.txt | 4651 ZR{
|
| /third_party/mesa3d/docs/ |
| D | release-maintainers-keys.asc | 1039 3/XmkoxR1RzGp9rU4F1HH86qSpuGCB1rtb3S7S5UlU2SH+Ja5u+06W1JJ+ZR/EKp
|
| /third_party/flutter/engine/flutter/lib/web_ui/lib/src/ui/ |
| D | window.dart | 460 case 'ZR':
|
| /third_party/icu/icu4c/source/data/misc/ |
| D | langInfo.txt | 1869 "ZR","CD",
|
| D | metadata.txt | 5065 ZR{
|
| D | supplementalData.txt | 3611 "ZR",
7548 "ZR",
25989 017{"ZR"}
|
| /third_party/flutter/skia/third_party/externals/icu/source/data/misc/ |
| D | metadata.txt | 4424 ZR{
|
| D | supplementalData.txt | 3611 "ZR",
7288 "ZR",
25212 017{"ZR"}
|
| /third_party/skia/third_party/externals/icu/source/data/misc/ |
| D | langInfo.txt | 1871 "ZR","CD",
|
| D | metadata.txt | 5065 ZR{
|
| D | supplementalData.txt | 3611 "ZR",
7548 "ZR",
25989 017{"ZR"}
|
| /third_party/flutter/engine/flutter/lib/ui/ |
| D | window.dart | 465 'ZR': 'CD', // Zaire; deprecated 1997-07-14
|