Home
last modified time | relevance | path

Searched refs:__u32 (Results 1 – 25 of 302) sorted by relevance

12345678910>>...13

/third_party/e2fsprogs/ext2ed/
Dext2.descriptors60 __u32 bg_block_bitmap; /* Blocks bitmap block */
61 __u32 bg_inode_bitmap; /* Inodes bitmap block */
62 __u32 bg_inode_table; /* Inodes table block */
67 __u32 bg_reserved[0];
68 __u32 bg_reserved[1];
69 __u32 bg_reserved[2];
78 __u32 i_size; /* Size in bytes */
79 __u32 i_atime; /* Access time */
80 __u32 i_ctime; /* Creation time */
81 __u32 i_mtime; /* Modification time */
[all …]
/third_party/mesa3d/include/drm-uapi/
Ddrm_mode.h243 __u32 clock;
255 __u32 vrefresh;
257 __u32 flags;
258 __u32 type;
267 __u32 count_fbs;
268 __u32 count_crtcs;
269 __u32 count_connectors;
270 __u32 count_encoders;
271 __u32 min_width;
272 __u32 max_width;
[all …]
Damdgpu_drm.h157 __u32 handle;
158 __u32 _pad;
175 __u32 operation;
177 __u32 list_handle;
179 __u32 bo_number;
181 __u32 bo_info_size;
188 __u32 bo_handle;
190 __u32 bo_priority;
195 __u32 list_handle;
196 __u32 _pad;
[all …]
Dvirtgpu_drm.h63 __u32 handle;
64 __u32 pad;
68 __u32 flags;
69 __u32 size;
72 __u32 num_bo_handles;
74 __u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
75 __u32 pad;
94 __u32 target;
95 __u32 format;
96 __u32 bind;
[all …]
Dtegra_drm.h57 __u32 flags;
65 __u32 handle;
77 __u32 handle;
84 __u32 pad;
104 __u32 id;
112 __u32 value;
124 __u32 id;
131 __u32 pad;
143 __u32 id;
150 __u32 thresh;
[all …]
Dvc4_drm.h66 __u32 hindex; /* Handle index, or ~0 if not present. */
67 __u32 offset; /* Offset to start of buffer. */
130 __u32 bin_cl_size;
132 __u32 shader_rec_size;
139 __u32 shader_rec_count;
141 __u32 uniforms_size;
144 __u32 bo_handle_count;
159 __u32 clear_color[2];
160 __u32 clear_z;
163 __u32 pad:24;
[all …]
Dlima_drm.h30 __u32 param; /* in, value in enum drm_lima_param */
31 __u32 pad; /* pad, must be zero */
46 __u32 size; /* in, buffer size */
47 __u32 flags; /* in, buffer flags */
48 __u32 handle; /* out, GEM buffer handle */
49 __u32 pad; /* pad, must be zero */
56 __u32 handle; /* in, GEM buffer handle */
57 __u32 va; /* out, virtual address mapped into GPU MMU */
66 __u32 handle; /* in, GEM buffer handle */
67 __u32 flags; /* in, buffer read/write by GPU */
[all …]
Dv3d_drm.h90 __u32 bcl_start;
93 __u32 bcl_end;
106 __u32 rcl_start;
109 __u32 rcl_end;
112 __u32 in_sync_bcl;
114 __u32 in_sync_rcl;
116 __u32 out_sync;
123 __u32 qma;
126 __u32 qms;
129 __u32 qts;
[all …]
Dmsm_drm.h90 __u32 pipe; /* in, MSM_PIPE_x */
91 __u32 param; /* in, MSM_PARAM_x */
114 __u32 flags; /* in, mask of MSM_BO_x */
115 __u32 handle; /* out */
131 __u32 handle; /* in */
132 __u32 info; /* in - one of MSM_INFO_* */
134 __u32 len; /* in or out */
135 __u32 pad;
145 __u32 handle; /* in */
146 __u32 op; /* in, mask of MSM_PREP_x */
[all …]
Di915_drm.h118 __u32 name;
124 __u32 flags;
130 __u32 rsvd[4];
313 __u32 unused1, unused2, unused3;
318 __u32 front_bo_handle;
319 __u32 back_bo_handle;
320 __u32 unused_bo_handle;
321 __u32 depth_bo_handle;
788 __u32 handle;
789 __u32 pad;
[all …]
/third_party/libdrm/include/drm/
Ddrm_mode.h213 __u32 clock;
225 __u32 vrefresh;
227 __u32 flags;
228 __u32 type;
237 __u32 count_fbs;
238 __u32 count_crtcs;
239 __u32 count_connectors;
240 __u32 count_encoders;
241 __u32 min_width;
242 __u32 max_width;
[all …]
Damdgpu_drm.h149 __u32 handle;
150 __u32 _pad;
167 __u32 operation;
169 __u32 list_handle;
171 __u32 bo_number;
173 __u32 bo_info_size;
180 __u32 bo_handle;
182 __u32 bo_priority;
187 __u32 list_handle;
188 __u32 _pad;
[all …]
Dvmwgfx_drm.h118 __u32 param;
119 __u32 pad64;
141 __u32 pad64;
183 __u32 flags;
184 __u32 format;
185 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
219 __u32 width;
220 __u32 height;
221 __u32 depth;
222 __u32 pad64;
[all …]
Dtegra_drm.h57 __u32 flags;
65 __u32 handle;
77 __u32 handle;
84 __u32 pad;
104 __u32 id;
112 __u32 value;
124 __u32 id;
131 __u32 pad;
143 __u32 id;
150 __u32 thresh;
[all …]
Dvc4_drm.h66 __u32 hindex; /* Handle index, or ~0 if not present. */
67 __u32 offset; /* Offset to start of buffer. */
130 __u32 bin_cl_size;
132 __u32 shader_rec_size;
139 __u32 shader_rec_count;
141 __u32 uniforms_size;
144 __u32 bo_handle_count;
159 __u32 clear_color[2];
160 __u32 clear_z;
163 __u32 pad:24;
[all …]
Dvirtgpu_drm.h59 __u32 handle;
60 __u32 pad;
64 __u32 flags;
65 __u32 size;
68 __u32 num_bo_handles;
83 __u32 target;
84 __u32 format;
85 __u32 bind;
86 __u32 width;
87 __u32 height;
[all …]
Di915_drm.h82 __u32 name;
83 __u32 flags; /* All undefined bits must be zero. */
84 __u32 rsvd[4]; /* Reserved for future use; must be zero. */
252 __u32 unused1, unused2, unused3;
257 __u32 front_bo_handle;
258 __u32 back_bo_handle;
259 __u32 unused_bo_handle;
260 __u32 depth_bo_handle;
688 __u32 handle;
689 __u32 pad;
[all …]
/third_party/libnl/include/linux-private/linux/
Dpkt_sched.h35 __u32 packets; /* Number of enqueued packets */
36 __u32 drops; /* Packets dropped because of lack of resources */
37 __u32 overlimits; /* Number of throttle events when this
39 __u32 bps; /* Current flow byte rate */
40 __u32 pps; /* Current flow packet rate */
41 __u32 qlen;
42 __u32 backlog;
96 __u32 rate;
124 __u32 limit; /* Queue length: bytes for bfifo, packets for pfifo */
139 __u32 limit; /* Queue length in packets. */
[all …]
/third_party/ntfs-3g/include/fuse-lite/
Dfuse_kernel.h41 #define __u32 uint32_t macro
85 __u32 atimensec;
86 __u32 mtimensec;
87 __u32 ctimensec;
88 __u32 mode;
89 __u32 nlink;
90 __u32 uid;
91 __u32 gid;
92 __u32 rdev;
102 __u32 bsize;
[all …]
/third_party/e2fsprogs/lib/blkid/
Dprobe.h54 __u32 s_inodes_count;
55 __u32 s_blocks_count;
56 __u32 s_r_blocks_count;
57 __u32 s_free_blocks_count;
58 __u32 s_free_inodes_count;
59 __u32 s_first_data_block;
60 __u32 s_log_block_size;
61 __u32 s_dummy3[7];
64 __u32 s_dummy5[8];
65 __u32 s_feature_compat;
[all …]
/third_party/mesa3d/src/gallium/winsys/svga/drm/
Dvmwgfx_drm.h134 __u32 param;
135 __u32 pad64;
157 __u32 pad64;
199 __u32 flags;
200 __u32 format;
201 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
235 __u32 width;
236 __u32 height;
237 __u32 depth;
238 __u32 pad64;
[all …]
/third_party/gstreamer/gstplugins_bad/sys/v4l2codecs/linux/
Dvideodev2.h80 ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))
409 __u32 width;
410 __u32 height;
414 __u32 numerator;
415 __u32 denominator;
419 __u32 width;
420 __u32 height;
438 __u32 version;
439 __u32 capabilities;
440 __u32 device_caps;
[all …]
Dmedia.h31 __u32 media_version;
32 __u32 hw_revision;
33 __u32 driver_version;
34 __u32 reserved[31];
150 __u32 id;
152 __u32 type;
153 __u32 revision;
154 __u32 flags;
155 __u32 group_id;
159 __u32 reserved[4];
[all …]
/third_party/gstreamer/gstplugins_good/sys/v4l2/ext/
Dvideodev2.h80 ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))
409 __u32 width;
410 __u32 height;
414 __u32 numerator;
415 __u32 denominator;
419 __u32 width;
420 __u32 height;
438 __u32 version;
439 __u32 capabilities;
440 __u32 device_caps;
[all …]
/third_party/libdrm/etnaviv/
Detnaviv_drm.h80 __u32 pipe; /* in */
81 __u32 param; /* in, ETNAVIV_PARAM_x */
99 __u32 flags; /* in, mask of ETNA_BO_x */
100 __u32 handle; /* out */
104 __u32 handle; /* in */
105 __u32 pad;
114 __u32 handle; /* in */
115 __u32 op; /* in, mask of ETNA_PREP_x */
120 __u32 handle; /* in */
121 __u32 flags; /* in, placeholder for now, no defined values */
[all …]

12345678910>>...13