| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 20 TmpInst.addOperand(MCOp);
22 TmpInst.addOperand(MCOperand::createImm(14));
23 TmpInst.addOperand(MCOperand::createReg(0));
33 TmpInst.addOperand(MCOp);
36 TmpInst.addOperand(MCOp);
39 TmpInst.addOperand(MCOp);
41 TmpInst.addOperand(MCOp);
44 TmpInst.addOperand(MCOp);
48 TmpInst.addOperand(MCOp);
58 TmpInst.addOperand(MCOp);
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 20 TmpInst.addOperand(MCOp);
23 TmpInst.addOperand(MCOp);
26 TmpInst.addOperand(MCOp);
36 TmpInst.addOperand(MCOp);
39 TmpInst.addOperand(MCOp);
42 TmpInst.addOperand(MCOp);
52 TmpInst.addOperand(MCOp);
55 TmpInst.addOperand(MCOp);
58 TmpInst.addOperand(MCOp);
67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 622 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
628 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
642 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
656 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATI()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 415 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
420 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
425 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
430 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
449 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
454 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
459 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); in addRegVFRCOperands()
464 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
469 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
474 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 246 ITInst.addOperand(MCOperand::createImm(ITState.Cond)); in flushPendingInstructions()
247 ITInst.addOperand(MCOperand::createImm(ITState.Mask)); in flushPendingInstructions()
2325 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
2327 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
2329 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
2344 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2346 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
2351 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred()))); in addVPTPredNOperands()
2353 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredNOperands()
2370 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredROperands()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 215 CompoundInsn->addOperand(Rt); in getCompoundInsn()
216 CompoundInsn->addOperand(L.getOperand(1)); // Immediate in getCompoundInsn()
217 CompoundInsn->addOperand(R.getOperand(0)); // Jump target in getCompoundInsn()
227 CompoundInsn->addOperand(Rt); in getCompoundInsn()
228 CompoundInsn->addOperand(Rs); in getCompoundInsn()
229 CompoundInsn->addOperand(R.getOperand(0)); // Jump target. in getCompoundInsn()
241 CompoundInsn->addOperand(Rs); in getCompoundInsn()
242 CompoundInsn->addOperand(Rt); in getCompoundInsn()
243 CompoundInsn->addOperand(R.getOperand(1)); in getCompoundInsn()
254 CompoundInsn->addOperand(Rs); in getCompoundInsn()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 252 T.addOperand(Inst.getOperand(i)); in ScaleVectorOffset()
260 T.addOperand(MCOperand::createExpr(NewHE)); in ScaleVectorOffset()
284 Inst.addOperand(Reg); in HexagonProcessInstruction()
285 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
286 Inst.addOperand(S16); in HexagonProcessInstruction()
293 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
300 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
307 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
314 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
321 Inst.addOperand(MCOperand::createExpr(C255)); in HexagonProcessInstruction()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInstBuilder.h | 32 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
38 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
44 Inst.addOperand(MCOperand::createFPImm(Val)); in addFPImm()
50 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
56 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
61 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function
62 Inst.addOperand(Op); in addOperand()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 67 Inst.addOperand(MCOperand::createImm(Offset)); in DecodePCRel24BranchTarget()
78 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
182 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
190 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
213 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
224 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); in decodeMemRIOperands()
225 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
241 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
245 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); in decodeMemRIXOperands()
246 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 88 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
174 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
182 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
256 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand()
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
297 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
307 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
318 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.cpp | 38 NopInst.addOperand(MCOperand::createImm(0)); in getNoop()
39 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoop()
40 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
43 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoop()
45 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoop()
46 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 92 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
123 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm()
128 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm()
133 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm()
139 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
144 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex()
151 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
157 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
164 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
171 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
179 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
181 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeRiMemoryValue()
191 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
203 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
205 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset))); in decodeSplsValue()
223 MI.addOperand(MCOperand::createImm(Insn)); in decodeBranch()
230 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeShiftImm()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixupVectorISel.cpp | 188 NewGlob->addOperand(MF, MI.getOperand(0)); in fixupGlobalSaddr()
189 NewGlob->addOperand(MF, MachineOperand::CreateReg(IndexReg, false)); in fixupGlobalSaddr()
191 NewGlob->addOperand(MF, *VData); in fixupGlobalSaddr()
192 NewGlob->addOperand(MF, MachineOperand::CreateReg(BaseReg, false)); in fixupGlobalSaddr()
193 NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::offset)); in fixupGlobalSaddr()
198 NewGlob->addOperand(MF, *Glc); in fixupGlobalSaddr()
202 NewGlob->addOperand(MF, *DLC); in fixupGlobalSaddr()
204 NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::slc)); in fixupGlobalSaddr()
209 NewGlob->addOperand(MF, *VDstInOp); in fixupGlobalSaddr()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 321 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR128RegisterClass()
350 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR64RegisterClass()
371 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR32RegisterClass()
392 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR16RegisterClass()
413 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR8RegisterClass()
434 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64commonRegisterClass()
445 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64RegisterClass()
457 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64spRegisterClass()
478 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32RegisterClass()
491 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32spRegisterClass()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1133 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass()
1147 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCLRMGPRRegisterClass()
1171 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
1186 Inst.addOperand(MCOperand::createReg(ARM::ZR)); in DecodeGPRwithZRRegisterClass()
1230 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeGPRPairRegisterClass()
1241 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRspRegisterClass()
1271 Inst.addOperand(MCOperand::createReg(Register)); in DecodetcGPRRegisterClass()
1306 Inst.addOperand(MCOperand::createReg(Register)); in DecodeSPRRegisterClass()
1337 Inst.addOperand(MCOperand::createReg(Register)); in DecodeDPRRegisterClass()
1377 Inst.addOperand(MCOperand::createReg(Register)); in DecodeQPRRegisterClass()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 380 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
385 Inst.addOperand(MCOperand::createExpr(getImm())); in addImmOperands()
394 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
404 Inst.addOperand(MCOperand::createExpr(NewExpr)); in addSignedImmOperands()
537 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in canonicalizeImmediates()
543 NewInst.addOperand(I); in canonicalizeImmediates()
613 MCB.addOperand(MCOperand::createImm(0)); in MatchAndEmitInstruction()
646 MCB.addOperand(MCOperand::createInst(SubInst)); in MatchAndEmitInstruction()
1227 TmpInst.addOperand(Rdd); in makeCombineInst()
1228 TmpInst.addOperand(MO1); in makeCombineInst()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Disassembler/ |
| D | RISCVDisassembler.cpp | 72 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
83 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
94 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
105 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
116 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
147 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass()
174 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
193 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
214 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1))); in decodeSImmOperandAndLsl1()
225 Inst.addOperand(MCOperand::createImm(Imm)); in decodeCLUIImmOperand()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 170 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
180 TmpInst.addOperand(Op1); in emitRX()
199 TmpInst.addOperand(MCOperand::createImm(Imm1)); in emitII()
200 TmpInst.addOperand(MCOperand::createImm(Imm2)); in emitII()
210 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
211 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
212 TmpInst.addOperand(Op2); in emitRRX()
228 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX()
229 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 953 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
954 MOVI.addOperand(MCOperand::createImm(0)); in EmitFMov0()
962 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
963 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
967 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
968 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
972 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
973 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in EmitFMov0()
1037 MovZ.addOperand(MCOperand::createReg(DestReg)); in EmitInstruction()
1038 MovZ.addOperand(Hi_MCSym); in EmitInstruction()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 489 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
491 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
496 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
504 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
538 Inst.addOperand(MCOperand::createReg(Reg)); in addMaskPairOperands()
543 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands()
544 Inst.addOperand(MCOperand::createImm(getMemScale())); in addMemOperands()
545 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands()
547 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands()
554 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addAbsMemOperands()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/MCTargetDesc/ |
| D | RISCVAsmBackend.cpp | 89 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
90 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
91 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
96 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
97 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
98 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
103 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
104 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
109 Res.addOperand(MCOperand::createReg(RISCV::X1)); in relaxInstruction()
110 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 152 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeIntRegsRegisterClass()
163 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegsRegisterClass()
175 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRegsRegisterClass()
187 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeDFPRegsRegisterClass()
202 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeQFPRegsRegisterClass()
213 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeCPRegsRegisterClass()
222 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); in DecodeFCCRegsRegisterClass()
231 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); in DecodeASRRegsRegisterClass()
240 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); in DecodePRRegsRegisterClass()
255 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeIntPairRegisterClass()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/Disassembler/ |
| D | ARCDisassembler.cpp | 129 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
164 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9))); in DecodeMEMrs9()
183 Inst.addOperand(MCOperand::createImm(Offset)); in DecodeSymbolicOperandOff()
201 Inst.addOperand(MCOperand::createImm( in DecodeSignedOperand()
213 Inst.addOperand( in DecodeFromCyclicRange()
230 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeStLImmInstruction()
231 Inst.addOperand(MCOperand::createImm(0)); in DecodeStLImmInstruction()
248 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeLdLImmInstruction()
249 Inst.addOperand(MCOperand::createImm(0)); in DecodeLdLImmInstruction()
266 Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> 32))); in DecodeLdRLImmInstruction()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/Disassembler/ |
| D | BPFDisassembler.cpp | 107 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
122 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
129 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeMemoryOpValue()
131 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeMemoryOpValue()
210 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
211 Instr.addOperand(Op); in getInstruction()
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