| /third_party/mesa3d/src/gallium/auxiliary/pipebuffer/ |
| D | pb_bufmgr_cache.c | 235 assert(pb_check_alignment(desc->alignment, 1u << buf->buffer->alignment_log2)); in pb_cache_manager_create_buffer()
239 buf->base.alignment_log2 = buf->buffer->alignment_log2; in pb_cache_manager_create_buffer()
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| D | pb_bufmgr_debug.c | 402 assert(pb_check_alignment(real_desc.alignment, 1u << buf->buffer->alignment_log2)); in pb_debug_manager_create_buffer()
407 buf->base.alignment_log2 = util_logbase2(desc->alignment); in pb_debug_manager_create_buffer()
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| D | pb_buffer.h | 124 uint8_t alignment_log2; member
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| D | pb_bufmgr_slab.c | 342 buf->base.alignment_log2 = 0; in pb_slab_create()
419 buf->base.alignment_log2 = util_logbase2(desc->alignment); in pb_slab_manager_create_buffer()
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| D | pb_bufmgr_mm.c | 196 mm_buf->base.alignment_log2 = util_logbase2(desc->alignment); in mm_bufmgr_create_buffer()
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| D | pb_cache.c | 136 if (!pb_check_alignment(alignment, 1u << buf->alignment_log2)) in pb_cache_is_buffer_compat()
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| D | pb_buffer_fenced.c | 911 fenced_buf->base.alignment_log2 = util_logbase2(desc->alignment); in fenced_bufmgr_create_buffer()
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | radeon_video.c | 192 size = align(size, 1 << (*buffers[i])->alignment_log2); in rvid_join_surfaces()
194 alignment = MAX2(alignment, 1 << (*buffers[i])->alignment_log2); in rvid_join_surfaces()
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| D | r600_state.c | 990 (1 << rctx->dummy_cmask->buf->alignment_log2) % cmask.alignment != 0) { in r600_init_color_surface()
1015 (1 << rctx->dummy_fmask->buf->alignment_log2) % fmask.alignment != 0) { in r600_init_color_surface()
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| D | r600_texture.c | 980 resource->bo_alignment = 1 << buf->alignment_log2; in r600_texture_create_object()
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| /third_party/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_bo.c | 588 bo->base.alignment_log2 = util_logbase2(alignment); in amdgpu_create_bo()
652 assert(bo->base.size < (1 << bo->base.alignment_log2) || in get_slab_wasted_size()
780 bo->base.alignment_log2 = util_logbase2(get_slab_entry_alignment(ws, entry_size)); in amdgpu_bo_slab_alloc()
1141 bo->base.alignment_log2 = util_logbase2(RADEON_SPARSE_PAGE_SIZE); in amdgpu_bo_sparse_create()
1427 assert(alignment <= 1 << bo->base.alignment_log2); in amdgpu_bo_create()
1583 bo->base.alignment_log2 = util_logbase2(info.phys_alignment); in amdgpu_bo_from_handle()
1727 bo->base.alignment_log2 = 0; in amdgpu_bo_from_ptr()
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| /third_party/mesa3d/src/gallium/drivers/zink/ |
| D | zink_bo.c | 280 bo->base.alignment_log2 = util_logbase2(alignment); in bo_create_internal()
504 bo->base.alignment_log2 = util_logbase2(ZINK_SPARSE_BUFFER_PAGE_SIZE); in bo_sparse_create()
585 assert(alignment <= 1 << bo->base.alignment_log2); in zink_bo_create()
892 bo->base.alignment_log2 = util_logbase2(get_slab_entry_alignment(screen, entry_size)); in bo_slab_alloc()
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| /third_party/mesa3d/src/gallium/winsys/svga/drm/ |
| D | vmw_buffer.c | 225 buf->base.alignment_log2 = util_logbase2(pb_desc->alignment); in vmw_gmr_bufmgr_create_buffer()
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| D | pb_buffer_simple_fenced.c | 734 fenced_buf->base.alignment_log2 = util_logbase2(desc->alignment); in fenced_bufmgr_create_buffer()
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| /third_party/mesa3d/src/gallium/drivers/d3d12/ |
| D | d3d12_bufmgr.cpp | 289 buf->base.alignment_log2 = util_logbase2(pb_desc->alignment); in d3d12_bufmgr_create_buffer()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_surface.h | 355 uint8_t alignment_log2; member
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| D | ac_surface.c | 2400 surf->alignment_log2 = surf->surf_alignment_log2; in ac_compute_surface()
2409 surf->alignment_log2 = MAX2(surf->alignment_log2, surf->fmask_alignment_log2); in ac_compute_surface()
2416 surf->alignment_log2 = MAX2(surf->alignment_log2, surf->cmask_alignment_log2); in ac_compute_surface()
2438 surf->alignment_log2 = MAX2(surf->alignment_log2, surf->meta_alignment_log2); in ac_compute_surface()
2454 surf->alignment_log2 = surf->surf_alignment_log2; in ac_surface_zero_dcc_fields()
2828 if (offset & ((1 << surf->alignment_log2) - 1) || in ac_surface_override_offset_stride()
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| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_bo.c | 672 bo->base.alignment_log2 = util_logbase2(alignment); in radeon_create_bo()
807 bo->base.alignment_log2 = util_logbase2(entry_size); in radeon_bo_slab_alloc()
1133 bo->base.alignment_log2 = 0; in radeon_winsys_bo_from_ptr()
1262 bo->base.alignment_log2 = 0; in radeon_winsys_bo_from_handle()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 1317 surf->alignment_log2 = MAX2(surf->alignment_log2, surf->cmask_alignment_log2); in radv_image_alloc_single_sample_cmask()
1570 offset = align64(image->size, 1 << image->planes[plane].surface.alignment_log2); in radv_image_create_layout()
1594 image->alignment = MAX2(image->alignment, 1 << image->planes[plane].surface.alignment_log2); in radv_image_create_layout()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_texture.c | 1007 resource->bo_alignment_log2 = imported_buf->alignment_log2; in si_texture_create_object()
1550 buf->alignment_log2 < tex->surface.alignment_log2) { in si_texture_from_winsys_buffer()
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| D | si_buffer.c | 669 res->bo_alignment_log2 = imported_buf->alignment_log2; in si_buffer_from_winsys_buffer()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.2.0.rst | 3478 - radeonsi: change si_resource::alignment to alignment_log2 for better packing
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| D | 21.1.0.rst | 3587 - gallium/pb: change pb_buffer::alignment to alignment_log2
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