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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td168 def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>;
439 def : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>;
440 def : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>;
441 def : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>;
442 def : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>;
443 def : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>;
444 def : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>;
447 def : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>;
448 def : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>;
449 def : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>;
[all …]
DAArch64SVEInstrInfo.td194 defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub", int_aarch64_sve_fsub>;
314 defm BIC_PPzPP : sve_int_pred_log<0b0001, "bic", int_aarch64_sve_bic_z>;
343 defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>;
389 defm LD1B_H : sve_mem_cld_ss<0b0001, "ld1b", Z_h, ZPR16, GPR64NoXZRshifted8>;
407 defm LDNF1B_H_IMM : sve_mem_cldnf_si<0b0001, "ldnf1b", Z_h, ZPR16>;
425 defm LDFF1B_H : sve_mem_cldff_ss<0b0001, "ldff1b", Z_h, ZPR16, GPR64shifted8>;
472 …defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", null_frag, nul…
494 …defm GLDFF1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0001, "ldff1sb", imm0_31, null_frag, …
507 …defm GLDFF1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0001, "ldff1sb", imm0_31, null_frag, …
524 defm GLDFF1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0001, "ldff1sb", null_frag, nxv2i8>;
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DAArch64InstrInfo.td844 let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in {
1015 def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]> {
1904 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
3419 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
3472 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
4488 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
4509 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
5500 defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">;
6345 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
DSVEInstrFormats.td1764 let Inst{15-12} = 0b0001;
2529 def _S : sve2_complex_int_arith<0b10, 0b0001, asm, ZPR32, ZPR8>;
2530 def _D : sve2_complex_int_arith<0b11, 0b0001, asm, ZPR64, ZPR16>;
DAArch64InstrFormats.td1840 let Inst{13-10} = 0b0001;
6978 let Inst{14-11} = 0b0001;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td271 defm : int_cond_alias<"e", 0b0001>;
288 defm : int_cond_alias<"eq", 0b0001>; // same as e
289 defm : int_cond_alias<"z", 0b0001>; // same as e
301 defm : fp_cond_alias<"ne", 0b0001>;
312 defm : fp_cond_alias<"nz", 0b0001>; // same as ne
324 defm : cp_cond_alias<"123", 0b0001>;
/third_party/vk-gl-cts/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp128 b0001 = 0x1, enumerator
147 { false, false, false, b0001, b1000, b1111, false, NONE },
148 { true, false, false, b0001, b1000, b0000, false, NONE },
149 { true, false, false, b0001, b0001, b1110, false, NONE },
154 { true, true, true, b0010, b1000, b0001, false, NONE },
/third_party/flutter/skia/third_party/externals/wuffs/std/deflate/
DREADME.md310 0b0001 32
419 0b0001 32 (ASCII ' ')
441 0b0001 32 (ASCII ' ')
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td983 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
984 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
985 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
986 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
987 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
988 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
1151 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1187 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
2062 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
2063 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
[all …]
DARMInstrVFP.td922 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
927 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
936 def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,
1023 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
1029 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
1035 def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0,
2341 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
2346 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins),
2426 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$Rt),
2733 defm VSTR_FPSCR : vfp_vstrldr_sysreg<0b0,0b0001, "fpscr">;
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DARMInstrThumb2.td1267 let Inst{26-23} = 0b0001;
2418 def t2QADD16 : T2I_pam_intrinsics<0b001, 0b0001, "qadd16", int_arm_qadd16>;
2419 def t2QADD8 : T2I_pam_intrinsics<0b000, 0b0001, "qadd8", int_arm_qadd8>;
2420 def t2QASX : T2I_pam_intrinsics<0b010, 0b0001, "qasx", int_arm_qasx>;
2422 def t2QSAX : T2I_pam_intrinsics<0b110, 0b0001, "qsax", int_arm_qsax>;
2423 def t2QSUB16 : T2I_pam_intrinsics<0b101, 0b0001, "qsub16", int_arm_qsub16>;
2424 def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>;
2670 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2882 def t2MLS: T2FourRegMLA<0b0001, "mls",
2921 T2SMMUL<0b0001, "smmulr",
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DARMInstrInfo.td2483 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2514 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2634 let Inst{27-24} = 0b0001;
2644 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
3854 let Inst{7-4} = 0b0001;
3869 let Inst{7-4} = 0b0001;
3960 defm EOR : AsI1_bin_irs<0b0001, "eor",
4248 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4264 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
4538 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
[all …]
DARMInstrThumb.td1135 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
DARMInstrFormats.td1056 let Inst{7-4} = 0b0001;
DARMInstrMVE.td1411 def MVE_VORRIZ0v4i32 : MVE_VORR<"i32", 0b0001, expzero00>;
1440 def MVE_VBICIZ0v4i32 : MVE_VBIC<"i32", 0b0001, expzero00>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td669 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
670 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
681 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
682 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
773 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
774 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
1032 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1033 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1034 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1035 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
DMicroMips32r6InstrFormats.td720 let Inst{3-0} = 0b0001;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrInfo.td391 def ADCRdRr : FRdRr<0b0001,
432 def SUBRdRr : FRdRr<0b0001,
868 def CPSE : FRdRr<0b0001,
875 def CPRdRr : FRdRr<0b0001,
/third_party/skia/include/private/
DGrTypesPriv.h276 kLeft = 0b0001,
/third_party/skia/include/core/
DSkCanvas.h1576 kLeft_QuadAAFlag = 0b0001,
/third_party/flutter/skia/include/core/
DSkCanvas.h1811 kLeft_QuadAAFlag = 0b0001,
/third_party/mesa3d/src/freedreno/.gitlab-ci/reference/
DdEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log662 000000000115e244: 0000: 409b0001 00000000
Dfd-clouds.log816 0000000001123020: 0020: 40809583 00000000 00000000 00000000 409b0001 00000002
835 0000000001123030: 0000: 409b0001 00000002
5057 0000000001123020: 0020: 40809583 00000000 00000000 00000000 409b0001 00000002
5076 0000000001123030: 0000: 409b0001 00000002
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrInfo.td8926 let Inst{24-21} = 0b0001;
24939 let Inst{6-3} = 0b0001;
30108 let Inst{13-10} = 0b0001;