Searched refs:b0101 (Results 1 – 21 of 21) sorted by relevance
169 def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>;170 def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>;466 def : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>;467 def : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>;468 def : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>;469 def : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>;480 def : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>;481 def : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>;486 def : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>;487 def : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>;[all …]
198 defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm", int_aarch64_sve_fminnm>;318 defm BICS_PPzPP : sve_int_pred_log<0b0101, "bics", null_frag>;347 defm LD1H_IMM : sve_mem_cld_si<0b0101, "ld1h", Z_h, ZPR16>;393 defm LD1H : sve_mem_cld_ss<0b0101, "ld1h", Z_h, ZPR16, GPR64NoXZRshifted16>;411 defm LDNF1H_IMM : sve_mem_cldnf_si<0b0101, "ldnf1h", Z_h, ZPR16>;429 defm LDFF1H : sve_mem_cldff_ss<0b0101, "ldff1h", Z_h, ZPR16, GPR64shifted16>;476 …defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", null_frag, nul…485 …defm GLDFF1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0101, "ldff1sh", null_frag, …498 …defm GLDFF1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0101, "ldff1sh", uimm5s2, null_frag, …511 …defm GLDFF1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0101, "ldff1sh", uimm5s2, null_frag, …[all …]
1477 def GMI : BaseTwoOperand<0b0101, GPR64, "gmi", int_aarch64_gmi, GPR64sp>, Sched<[]>{1896 def DRPS : SpecialReturn<0b0101, "drps">;3477 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminimum>;4482 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",4505 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",5501 defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">;6305 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
7038 : BaseSIMDMov<Q, size, 0b0101, regtype, idxtype, "smov", []>;
171 let IClass = 0b0101;193 let IClass = 0b0101;227 let IClass = 0b0101;287 let IClass = 0b0101;344 let IClass = 0b0101;
9212 let Inst{24-21} = 0b0101;17721 let Inst{24-21} = 0b0101;17811 let Inst{24-21} = 0b0101;17859 let Inst{24-21} = 0b0101;20781 let Inst{24-21} = 0b0101;21281 let Inst{24-21} = 0b0101;21554 let Inst{24-21} = 0b0101;26137 let Inst{12-9} = 0b0101;
279 defm : int_cond_alias<"cs", 0b0101>;291 defm : int_cond_alias<"lu", 0b0101>; // same as cs297 defm : fp_cond_alias<"ug", 0b0101>;320 defm : cp_cond_alias<"23", 0b0101>;
923 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;924 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;925 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;926 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;927 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;928 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;1154 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {1166 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {1190 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {1201 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {[all …]
613 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,621 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,633 def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,641 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,649 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,661 def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0,2361 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPRnopc:$Rt), (ins),
2393 let Inst{26-23} = 0b0101;2421 def t2UQSUB8 : T2I_pam_intrinsics<0b100, 0b0101, "uqsub8", int_arm_uqsub8>;2425 def t2UQADD16 : T2I_pam_intrinsics<0b001, 0b0101, "uqadd16", int_arm_uqadd16>;2426 def t2UQADD8 : T2I_pam_intrinsics<0b000, 0b0101, "uqadd8", int_arm_uqadd8>;2427 def t2UQASX : T2I_pam_intrinsics<0b010, 0b0101, "uqasx", int_arm_uqasx>;2428 def t2UQSAX : T2I_pam_intrinsics<0b110, 0b0101, "uqsax", int_arm_uqsax>;2429 def t2UQSUB16 : T2I_pam_intrinsics<0b101, 0b0101, "uqsub16", int_arm_uqsub16>;3505 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),3580 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
949 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
1294 T1LoadStore<0b0101, opcode> {
1415 def MVE_VORRIZ16v4i32 : MVE_VORR<"i32", 0b0101, expzero16>;1444 def MVE_VBICIZ16v4i32 : MVE_VBIC<"i32", 0b0101, expzero16>;
3687 defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>;
132 b0101 = 0x5, enumerator152 { true, true, false, b1010, b1010, b0101, false, NONE },
678 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;679 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;737 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;738 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;847 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;848 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;849 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;850 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;865 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;866 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
314 0b0101 259
771 00000000010542c0: 0140: 00ffff00 48800101 00000000 489b0101 00000008 48a80201 00000002 48910401960 00000000010542cc: 0000: 489b0101 00000008
597 0000000001121080: 0080: 48a80201 00000001 40930401 ff00ff00 489b0101 00000004 409b0301 00000000680 0000000001121090: 0000: 489b0101 000000041879 0000000001120080: 0080: 48a80201 00000001 40930401 ff00ff00 489b0101 00000004 409b0301 000000001974 0000000001120090: 0000: 489b0101 00000004
542 defm ADD : Arith<0b0101, "add", add, 1, []>;
452 def SUBIRdK : FRdK<0b0101,