Searched refs:b0111 (Results 1 – 20 of 20) sorted by relevance
53 def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>;54 def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>;55 def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>;56 def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>;57 def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>;58 def : AT<"S1E3W", 0b110, 0b0111, 0b1000, 0b001>;59 def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>;60 def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>;61 def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>;62 def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>;[all …]
200 defm FMIN_ZPmZ : sve_fp_2op_p_zds<0b0111, "fmin", int_aarch64_sve_fmin>;349 defm LD1H_D_IMM : sve_mem_cld_si<0b0111, "ld1h", Z_d, ZPR64>;395 defm LD1H_D : sve_mem_cld_ss<0b0111, "ld1h", Z_d, ZPR64, GPR64NoXZRshifted16>;413 defm LDNF1H_D_IMM : sve_mem_cldnf_si<0b0111, "ldnf1h", Z_d, ZPR64>;431 defm LDFF1H_D : sve_mem_cldff_ss<0b0111, "ldff1h", Z_d, ZPR64, GPR64shifted16>;478 …defm GLDFF1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0111, "ldff1h", null_frag, nul…487 …defm GLDFF1H_S : sve_mem_32b_gld_sv_32_scaled<0b0111, "ldff1h", null_frag, …500 …defm GLDFF1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0111, "ldff1h", uimm5s2, null_frag, …513 …defm GLDFF1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0111, "ldff1h", uimm5s2, null_frag, …530 …defm GLDFF1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0111, "ldff1h", null_frag, nxv2i16>;[all …]
3476 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>;3629 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",4484 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",5636 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",6307 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
7041 : BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov",9402 defm One : BaseSIMDLd1<NAME, "One", asm, "VecListOne", 16, 8, 0b0111>;9409 defm One : BaseSIMDSt1<NAME, "One", asm, "VecListOne", 16, 8, 0b0111>;
226 #define BIFROST_FMTC_FINAL 0b0111
283 defm : int_cond_alias<"vs", 0b0111>;295 defm : fp_cond_alias<"u", 0b0111>;318 defm : cp_cond_alias<"3", 0b0111>;
108 return 0b0111; /* RGB */ in blend_factor_constant_mask()
624 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),652 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),660 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),1301 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {1314 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {1342 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {1354 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {1686 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),1712 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),1720 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),[all …]
742 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr,785 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr,1274 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1021 let Inst{7-4} = 0b0111;1289 // 0b0111 => Immediate, 1 byte
670 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,2356 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPRnopc:$Rt), (ins),
2088 let Inst{7-4} = 0b0111;2100 let Inst{7-4} = 0b0111;2637 let Inst{7-4} = 0b0111;3698 defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>;
1416 def MVE_VORRIZ24v4i32 : MVE_VORR<"i32", 0b0111, expzero24>;1445 def MVE_VBICIZ24v4i32 : MVE_VBIC<"i32", 0b0111, expzero24>;3579 let Inst{11-8} = 0b0111;5686 let Inst{12-9} = 0b0111;
3525 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),3606 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
183 src_mask = 0b0111; in ppir_emit_alu()
134 b0111 = 0x7, enumerator
675 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;676 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;693 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;694 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
549 defm SUBC : Arith<0b0111, "subc", sube, 0, [SR]>;
669 def ANDIRdK : FRdK<0b0111,
9026 let Inst{24-21} = 0b0111;