Searched refs:b1011 (Results 1 – 18 of 18) sorted by relevance
835 def BIT8rr : I8rr<0b1011,840 def BIT16rr : I16rr<0b1011,846 def BIT8rc : I8rc<0b1011,851 def BIT16rc : I16rc<0b1011,857 def BIT8ri : I8ri<0b1011,862 def BIT16ri : I16ri<0b1011,868 def BIT8rm : I8rm<0b1011,873 def BIT16rm : I16rm<0b1011,879 def BIT8rn : I8rn<0b1011, (outs), (ins GR8:$rd, indreg:$rs),881 def BIT16rn : I16rn<0b1011, (outs), (ins GR16:$rd, indreg:$rs),[all …]
119 def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>;629 def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>;637 def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>;650 def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>;662 def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>;663 def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>;664 def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>;665 def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>;719 def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>;720 def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>;[all …]
323 defm NAND_PPzPP : sve_int_pred_log<0b1011, "nand", int_aarch64_sve_nand_z>;353 defm LD1W_D_IMM : sve_mem_cld_si<0b1011, "ld1w", Z_d, ZPR64>;399 defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64NoXZRshifted32>;417 defm LDNF1W_D_IMM : sve_mem_cldnf_si<0b1011, "ldnf1w", Z_d, ZPR64>;435 defm LDFF1W_D : sve_mem_cldff_ss<0b1011, "ldff1w", Z_d, ZPR64, GPR64shifted32>;480 …defm GLDFF1W : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w", null_frag, nul…489 …defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", null_frag, …502 …defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4, null_frag, …517 …defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4, null_frag, …534 …defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w", null_frag, nxv2i32>;[all …]
3432 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;4497 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",5642 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
688 // Special case encoding: bits 11-8 is 0b1011.705 let Inst{11-8} = 0b1011;1121 def VMOVRRD : AVConv3I<0b11000101, 0b1011,1178 def VMOVDRR : AVConv5I<0b11000100, 0b1011,1357 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,1403 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,1507 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,1554 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,1603 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,1628 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,[all …]
1304 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {1317 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {1345 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {1357 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {2359 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {2372 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {2398 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {2410 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {4383 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,4408 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,[all …]
2074 let Inst{7-4} = 0b1011;2360 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func),2370 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func),2678 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,2805 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;2939 defm LDRHT : AI3ldrT<0b1011, "ldrht">;2960 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,3098 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),3112 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),3270 defm STRHT : AI3strT<0b1011, "strht">;[all …]
1086 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),1092 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1315 let Inst{15-12} = 0b1011;1690 let Inst{11-8} = 0b1011;
2294 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube>;2433 def t2QDSUB : T2I_pam_intrinsics_rev<0b000, 0b1011, "qdsub">;3049 def t2SMLALTT : T2MlaLong<0b100, 0b1011, "smlaltt">,5402 def t2CSNEG : CS<"csneg", 0b1011>;
1414 def MVE_VORRIZ8v8i16 : MVE_VORR<"i16", 0b1011, expzero08>;1443 def MVE_VBICIZ8v8i16 : MVE_VBIC<"i16", 0b1011, expzero08>;1494 let Inst{11-8} = 0b1011;2011 let Inst{11-8} = 0b1011;
274 defm : int_cond_alias<"ge", 0b1011>;304 defm : fp_cond_alias<"ge", 0b1011>;327 defm : cp_cond_alias<"02", 0b1011>;
420 let Inst{3-0} = 0b1011;
386 0b1011 12
138 b1011 = 0xB, enumerator
764 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;765 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;776 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;777 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
236 class SC_MMR6_ENC : POOL32C_LL_E_SC_E_FM_MMR6<"sc", 0b1011, 0b000>;
214 let Inst{31-28} = 0b1011;2661 let Inst{13-10} = 0b1011;2717 let Inst{13-10} = 0b1011;2773 let Inst{13-10} = 0b1011;2829 let Inst{13-10} = 0b1011;2885 let Inst{13-10} = 0b1011;2941 let Inst{13-10} = 0b1011;9907 let Inst{24-21} = 0b1011;10013 let Inst{24-21} = 0b1011;17675 let Inst{24-21} = 0b1011;[all …]