Searched refs:b1110 (Results 1 – 22 of 22) sorted by relevance
120 def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>;121 def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>;133 def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>;137 def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>;142 def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>;146 def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>;558 def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>;612 def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>;613 def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>;632 def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>;[all …]
326 defm NORS_PPzPP : sve_int_pred_log<0b1110, "nors", null_frag>;356 defm LD1SB_H_IMM : sve_mem_cld_si<0b1110, "ld1sb", Z_h, ZPR16>;402 defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>;420 defm LDNF1SB_H_IMM : sve_mem_cldnf_si<0b1110, "ldnf1sb", Z_h, ZPR16>;438 defm LDFF1SB_H : sve_mem_cldff_ss<0b1110, "ldff1sb", Z_h, ZPR16, GPR64shifted8>;518 …defm GLD1D : sve_mem_64b_gld_vi_64_ptrs<0b1110, "ld1d", uimm5s8, AArch64ld1_gather_imm, …535 …defm GLD1D : sve_mem_64b_gld_vs2_64_unscaled<0b1110, "ld1d", AArch64ld1_gather, nxv2i64>;548 …defm GLD1D : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d", AArch64ld1_gather_scaled, ZP…565 …defm GLD1D : sve_mem_64b_gld_vs_32_unscaled<0b1110, "ld1d", AArch64ld1_gather_sxtw, AAr…578 …defm GLD1D : sve_mem_64b_gld_sv_32_scaled<0b1110, "ld1d", AArch64ld1_gather_sxtw_scaled, A…[all …]
1862 def _DtoS : sve2_fp_convert_precision<0b1110, asm, ZPR32, ZPR64>;2344 def _B : sve2_int_mla<0b00, { 0b1110, S }, asm, ZPR8, ZPR8>;2345 def _H : sve2_int_mla<0b01, { 0b1110, S }, asm, ZPR16, ZPR16>;2346 def _S : sve2_int_mla<0b10, { 0b1110, S }, asm, ZPR32, ZPR32>;2347 def _D : sve2_int_mla<0b11, { 0b1110, S }, asm, ZPR64, ZPR64>;2987 let Inst{15-12} = 0b1110;
3431 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;4481 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;5379 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",5391 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1110, V128,5451 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1110, V64, imm0_255,5455 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255,
7660 BaseSIMDIndexedTied<Q, U, 0b0, 0b10, 0b1110, RegType, RegType, V128,
20 0b1110() {}21 >0b1110 : Symbol(B[0b1110], Decl(emitClassDeclarationWithLiteralPropertyNameInES6.ts, 5, 15))
24 0b1110() {}25 >0b1110 : () => void
219 0b1110 17244 0b1110 17, 3 extra bits = 0b111 = 7249 0b1110 17, 3 extra bits = 0b010 = 2251 0b1110 17, 3 extra bits = 0b001 = 1
333 let Opcode = 0b1110;361 let Opcode = 0b1110;396 let Opcode = 0b1110;
280 defm : int_cond_alias<"pos", 0b1110>;307 defm : fp_cond_alias<"ule", 0b1110>;330 defm : cp_cond_alias<"013", 0b1110>;
1700 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,1712 def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1,1726 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,1744 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,1762 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,1772 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,2378 def VMRS_FPCXTNS : MovFromVFP<0b1110 /* fpcxtns */, (outs GPR:$Rt), (ins),2442 def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$Rt),2737 defm VSTR_FPCXTNS : vfp_vstrldr_sysreg<0b0,0b1110, "fpcxtns">;2755 defm VLDR_FPCXTNS : vfp_vstrldr_sysreg<0b1,0b1110, "fpcxtns">;
1537 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),1568 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),4439 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",4441 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary,4551 defm VQRDMLAHsl : N3VMulOpSL_HS<0b1110, IIC_VMACi16D, IIC_VMACi32D,5093 def VCEQfd : N3VD_cmp<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,5095 def VCEQfq : N3VQ_cmp<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,5097 def VCEQhd : N3VD_cmp<0,0,0b01,0b1110,0, IIC_VBIND, "vceq", "f16", v4i16, v4f16,5100 def VCEQhq : N3VQ_cmp<0,0,0b01,0b1110,0, IIC_VBINQ, "vceq", "f16", v8i16, v8f16,5113 def VCGEfd : N3VD_cmp<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,[all …]
2327 defm t2RSB : T2I_rbin_irs <0b1110, "rsb", sub>;4242 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc timm:$cop, timm:$CRd, addrmode5:$addr)]…4243 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr…4247 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc timm:$cop, timm:$CRd, addrmode5:$addr)]…4248 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr…4387 let Inst{27-24} = 0b1110;4431 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,4453 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,4477 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, (outs),4491 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),[all …]
2195 let Inst{31-28} = 0b1110; // AL2364 let Inst{31-28} = 0b1110;2632 let Inst{31-28} = 0b1110;3962 defm BIC : AsI1_bin_irs<0b1110, "bic",4634 let Inst{31-28} = 0b1110;5157 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,5181 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,5382 : ABI<0b1110, oops, iops, NoItinerary, opc,5427 : ABXI<0b1110, oops, iops, NoItinerary,
1075 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1418 let Inst{11-8} = 0b1110;
36 let Inst{22-19} = 0b1110;
725 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;726 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;758 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;759 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;941 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;942 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
141 b1110 = 0xE, enumerator149 { true, false, false, b0001, b0001, b1110, false, NONE },
547 defm XOR : Arith<0b1110, "xor", xor, 1, []>;
135 ('0b1110', '1110')137 ('0b1110', '1110')
1107 def LDIRdK : FRdK<0b1110,
9423 let Inst{24-21} = 0b1110;9515 let Inst{24-21} = 0b1110;13428 let Inst{13-10} = 0b1110;17585 let Inst{24-21} = 0b1110;20802 let Inst{24-21} = 0b1110;25943 let Inst{12-9} = 0b1110;26099 let Inst{12-9} = 0b1110;