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Searched refs:base_layer (Results 1 – 21 of 21) sorted by relevance

/third_party/weston/ivi-shell/
Dhmi-controller.c795 struct hmi_controller_layer *base_layer = NULL; in hmi_controller_create() local
820 base_layer = MEM_ALLOC(1 * sizeof(struct hmi_controller_layer)); in hmi_controller_create()
821 base_layer->x = 0; in hmi_controller_create()
822 base_layer->y = 0; in hmi_controller_create()
823 base_layer->width = output->current_mode->width; in hmi_controller_create()
824 base_layer->height = output->current_mode->height; in hmi_controller_create()
825 base_layer->id_layer = in hmi_controller_create()
828 wl_list_insert(&hmi_ctrl->base_layer_list, &base_layer->link); in hmi_controller_create()
830 create_layer(output, base_layer, hmi_ctrl); in hmi_controller_create()
913 struct hmi_controller_layer *base_layer = NULL; in ivi_hmi_controller_set_background() local
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/third_party/mesa3d/src/intel/vulkan/
Danv_blorp.c1056 unsigned base_layer = pRanges[r].baseArrayLayer; in anv_CmdClearColorImage() local
1068 base_layer = 0; in anv_CmdClearColorImage()
1075 base_layer, layer_count); in anv_CmdClearColorImage()
1079 level, base_layer, layer_count, in anv_CmdClearColorImage()
1135 unsigned base_layer = pRanges[r].baseArrayLayer; in anv_CmdClearDepthStencilImage() local
1150 level, base_layer, layer_count, in anv_CmdClearDepthStencilImage()
1162 level, base_layer, layer_count, in anv_CmdClearDepthStencilImage()
1533 uint32_t base_layer, uint32_t layer_count) in anv_image_copy_to_shadow() argument
1569 const uint32_t layer = base_layer + a; in anv_image_copy_to_shadow()
1591 uint32_t level, uint32_t base_layer, uint32_t layer_count, in anv_image_clear_color() argument
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DgenX_cmd_buffer.c502 uint32_t base_layer, uint32_t layer_count) in anv_image_init_aux_tt() argument
527 const uint32_t layer = base_layer + a; in anv_image_init_aux_tt()
604 uint32_t base_layer, uint32_t layer_count, in transition_depth_buffer() argument
620 0, 1, base_layer, layer_count); in transition_depth_buffer()
659 0, base_layer, layer_count, ISL_AUX_OP_FULL_RESOLVE); in transition_depth_buffer()
663 0, base_layer, layer_count, ISL_AUX_OP_AMBIGUATE); in transition_depth_buffer()
683 uint32_t base_layer, uint32_t layer_count, in transition_stencil_buffer() argument
714 base_layer, layer_count); in transition_stencil_buffer()
727 base_level, level_count, base_layer, layer_count); in transition_stencil_buffer()
747 MIN2(layer_count, aux_layers - base_layer); in transition_stencil_buffer()
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Danv_genX.h99 uint32_t base_layer,
Danv_private.h4221 uint32_t base_layer,
4230 uint32_t level, uint32_t base_layer, uint32_t layer_count,
4238 uint32_t base_layer, uint32_t layer_count,
4259 uint32_t base_layer, uint32_t layer_count,
4266 uint32_t base_layer, uint32_t layer_count,
4273 uint32_t base_layer, uint32_t layer_count,
4281 uint32_t base_layer, uint32_t layer_count,
4290 uint32_t base_layer, uint32_t layer_count);
Danv_cmd_buffer.c428 uint32_t base_layer, in anv_cmd_buffer_mark_image_written() argument
434 level, base_layer, in anv_cmd_buffer_mark_image_written()
/third_party/mesa3d/src/amd/vulkan/
Dradv_meta_resolve_cs.c817 .baseArrayLayer = src_iview->base_layer, in radv_cmd_buffer_resolve_subpass_cs()
824 .baseArrayLayer = dst_iview->base_layer, in radv_cmd_buffer_resolve_subpass_cs()
870 region.srcSubresource.baseArrayLayer = src_iview->base_layer; in radv_depth_stencil_resolve_subpass_cs()
894 .baseArrayLayer = src_iview->base_layer, in radv_depth_stencil_resolve_subpass_cs()
912 .baseArrayLayer = dst_iview->base_layer, in radv_depth_stencil_resolve_subpass_cs()
935 range.baseArrayLayer = dst_iview->base_layer; in radv_depth_stencil_resolve_subpass_cs()
Dradv_meta_resolve.c705 .baseArrayLayer = dest_iview->base_layer, in radv_cmd_buffer_resolve_subpass_hw()
883 region.srcSubresource.baseArrayLayer = src_iview->base_layer; in radv_decompress_resolve_subpass_src()
Dradv_image.c1839 hw_level + iview->level_count - 1, iview->base_layer, in radv_image_view_make_descriptor()
1840 iview->base_layer + iview->layer_count - 1, in radv_image_view_make_descriptor()
1919 if (iview->base_layer > 0 || iview->layer_count != image->info.array_size) in radv_image_view_can_fast_clear()
1957 iview->base_layer = range->baseArrayLayer; in radv_image_view_init()
Dradv_meta_clear.c667 iview->base_layer == 0 && iview->layer_count == iview->image->info.array_size && in depth_view_can_fast_clear()
1029 .baseArrayLayer = iview->base_layer, in radv_fast_clear_depth()
1862 .baseArrayLayer = iview->base_layer, in radv_fast_clear_color()
Dradv_cmd_buffer.c1826 .baseArrayLayer = iview->base_layer, in radv_emit_fb_color_state()
2094 .baseArrayLayer = iview->base_layer, in radv_update_tc_compat_zrange_metadata()
2119 .baseArrayLayer = iview->base_layer, in radv_update_ds_clear_metadata()
2310 .baseArrayLayer = iview->base_layer, in radv_update_color_clear_metadata()
4065 range.baseArrayLayer = view->base_layer; in radv_handle_subpass_image_transition()
Dradv_device.c6509 : (iview->base_layer + iview->layer_count); in radv_surface_max_layer_count()
6687 S_028C6C_SLICE_START(iview->base_layer) | S_028C6C_SLICE_MAX_GFX10(max_slice); in radv_initialise_color_surface()
6913 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) | S_028008_SLICE_MAX(max_slice); in radv_initialise_ds_surface()
6916 S_028008_SLICE_START_HI(iview->base_layer >> 11) | S_028008_SLICE_MAX_HI(max_slice >> 11); in radv_initialise_ds_surface()
Dradv_private.h2275 uint32_t base_layer; member
/third_party/mesa3d/src/gallium/drivers/softpipe/
Dsp_image.c39 int base_layer = 0; in get_image_offset() local
49 base_layer = r_coord + iview->u.tex.first_layer; in get_image_offset()
50 return softpipe_get_tex_image_offset(spr, iview->u.tex.level, base_layer); in get_image_offset()
/third_party/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_wm_surface_state.c1557 unsigned base_layer, num_layers; in update_image_surface() local
1560 base_layer = 0; in update_image_surface()
1564 base_layer = obj->Attrib.MinLayer; in update_image_surface()
1570 base_layer = obj->Attrib.MinLayer + u->_Layer; in update_image_surface()
1578 .base_array_layer = base_layer, in update_image_surface()
/third_party/mesa3d/src/intel/blorp/
Dblorp_priv.h187 uint32_t base_layer; member
Dblorp_clear.c248 nir_ssa_def *base_layer = nir_channel(&b, header, 0); in blorp_params_get_layer_offset_vs() local
250 nir_store_var(&b, v_layer, nir_iadd(&b, instance, base_layer), 0x1); in blorp_params_get_layer_offset_vs()
1168 params.vs_inputs.base_layer = start_layer; in blorp_clear_attachments()
/third_party/mesa3d/src/broadcom/vulkan/
Dv3dv_queue.c429 info->image_offset.x, info->image_offset.y, info->base_layer, in handle_copy_buffer_to_image_cpu_job()
436 v3dv_layer_offset(info->image, info->mip_level, info->base_layer + i); in handle_copy_buffer_to_image_cpu_job()
Dv3dv_private.h921 uint32_t base_layer; member
Dv3dv_meta_copy.c2675 job->cpu.copy_buffer_to_image.base_layer = in copy_buffer_to_image_cpu()
/third_party/mesa3d/src/gallium/frontends/lavapipe/
Dlvp_execute.c1314 int base_layer, int layer_count, in create_img_surface_bo() argument
1324 template.u.tex.first_layer = range->baseArrayLayer + base_layer; in create_img_surface_bo()
1338 int base_layer, int layer_count) in create_img_surface() argument
1341 … lvp_vk_format_to_pipe_format(format), width, height, base_layer, layer_count, 0); in create_img_surface()
1386 unsigned base_layer, unsigned layer_count, in clear_attachment_layers() argument
1396 base_layer, in clear_attachment_layers()
1397 base_layer + layer_count - 1); in clear_attachment_layers()