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Searched refs:bpe (Results 1 – 25 of 38) sorted by relevance

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/third_party/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_surface.c35 tileb = 8 * 8 * surf->bpe; in cik_get_macro_tile_index()
68 unsigned bpe) in surf_level_winsys_to_drm() argument
74 level_drm->pitch_bytes = level_ws->nblk_x * bpe; in surf_level_winsys_to_drm()
80 unsigned bpe) in surf_level_drm_to_winsys() argument
87 assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes); in surf_level_drm_to_winsys()
92 unsigned flags, unsigned bpe, in surf_winsys_to_drm() argument
108 surf_drm->bpe = bpe; in surf_winsys_to_drm()
158 bpe * surf_drm->nsamples); in surf_winsys_to_drm()
185 surf_ws->bpe = surf_drm->bpe; in surf_drm_to_winsys()
202 surf_drm->bpe * surf_drm->nsamples); in surf_drm_to_winsys()
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/third_party/libdrm/radeon/
Dradeon_surface.c169 unsigned bpe, unsigned level, in surf_minify() argument
191 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in surf_minify()
280 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
284 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_linear()
290 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear()
311 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
318 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear_aligned()
337 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
342 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_1d()
351 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_1d()
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Dradeon_surface.h119 uint32_t bpe; member
/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_surface.c65 unsigned flags, unsigned bpe, in amdgpu_surface_init() argument
78 surf->bpe = bpe; in amdgpu_surface_init()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_texture.c58 if (rdst->surface.bpe != rsrc->surface.bpe) in r600_prepare_for_dma_blit()
181 rtex->surface.bpe; in r600_texture_get_offset()
194 box->x / rtex->surface.blk_w) * rtex->surface.bpe; in r600_texture_get_offset()
211 unsigned i, bpe, flags = 0; in r600_init_surface() local
218 bpe = 4; /* stencil is allocated separately on evergreen */ in r600_init_surface()
220 bpe = util_format_get_blocksize(ptex->format); in r600_init_surface()
221 assert(util_is_power_of_two_or_zero(bpe)); in r600_init_surface()
248 flags, bpe, array_mode, surface); in r600_init_surface()
254 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) { in r600_init_surface()
258 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe; in r600_init_surface()
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Dradeon_vce.c234 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128); in rvce_frame_offset()
455 cpb_size = align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in rvce_create_encoder()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shaderlib_nir.c87 … ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.dcc_equation, in si_create_dcc_retile_cs()
95 …ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.display_dcc_equ… in si_create_dcc_retile_cs()
134 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, tex->surface.bpe, in gfx9_create_clear_dcc_msaa_cs()
Dsi_sdma_copy_image.c34 if (dst->surface.bpe != src->surface.bpe) in si_prepare_for_sdma_copy()
61 return util_logbase2(tex->surface.bpe) | in encode_legacy_tile_info()
115 unsigned bpp = sdst->surface.bpe; in si_sdma_v4_v5_copy_texture()
228 unsigned bpp = sdst->surface.bpe; in cik_sdma_copy_texture()
Dsi_texture.c126 *stride = tex->surface.u.gfx9.surf_pitch * tex->surface.bpe; in si_texture_get_offset()
138 tex->surface.bpe; in si_texture_get_offset()
140 *stride = tex->surface.u.legacy.level[level].nblk_x * tex->surface.bpe; in si_texture_get_offset()
153 tex->surface.bpe; in si_texture_get_offset()
165 unsigned bpe; in si_init_surface() local
172 bpe = 4; /* stencil is allocated separately */ in si_init_surface()
174 bpe = util_format_get_blocksize(ptex->format); in si_init_surface()
175 assert(util_is_power_of_two_or_zero(bpe)); in si_init_surface()
192 bpe = 4; in si_init_surface()
226 if (sscreen->info.family == CHIP_STONEY && bpe == 16 && ptex->nr_samples >= 2) in si_init_surface()
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Dsi_state_binning.c74 sum += tex->surface.bpe; in si_get_color_bin_size()
341 cColor += tex->surface.bpe * mmrt; in gfx10_get_bin_sizes()
Dsi_clear.c138 if (tex->surface.bpe == 16) { in si_set_clear_color()
430 switch (tex->surface.bpe) { in si_set_optimal_micro_tile_mode()
443 switch (tex->surface.bpe) { in si_set_optimal_micro_tile_mode()
637 !sctx->screen->allow_dcc_msaa_clear_to_reg_for_bpp[util_logbase2(tex->surface.bpe)]) in si_fast_clear()
673 if (tex->surface.bpe > 8) { in si_fast_clear()
/third_party/mesa3d/src/amd/common/
Dac_surface.c796 tileb = 8 * 8 * surf->bpe; in cik_get_macro_tile_index()
809 unsigned bpe = surf->bpe; in get_display_flag() local
826 (bpe >= 4 && bpe <= 8 && num_channels == 4) || in get_display_flag()
828 (bpe == 2 && num_channels >= 3) || in get_display_flag()
830 (bpe == 1 && num_channels == 1)) in get_display_flag()
1017 switch (surf->bpe) { in gfx6_compute_surface()
1028 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8; in gfx6_compute_surface()
1135 if (surf->bpe == 2) in gfx6_compute_surface()
1140 if (surf->bpe == 1) in gfx6_compute_surface()
1142 else if (surf->bpe == 2) in gfx6_compute_surface()
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Dac_surface.h311 uint8_t bpe : 5; member
480 unsigned bpe, struct gfx9_meta_equation *equation,
/third_party/mesa3d/src/gallium/drivers/radeon/
Dradeon_vce_40_2_2.c85 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch in create()
86 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch in create()
315 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
316 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
Dradeon_vce_52.c194 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch in create()
195 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch in create()
198 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encRefPicLumaPitch in create()
199 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encRefPicChromaPitch in create()
270 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
271 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
278 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encInputPicLumaPitch in encode()
279 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encInputPicChromaPitch in encode()
Dradeon_vce.c223 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128); in si_vce_frame_offset()
226 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256); in si_vce_frame_offset()
453 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in si_vce_create_encoder()
457 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in si_vce_create_encoder()
Dradeon_vce_50.c125 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
126 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
Dradeon_uvd_enc_1_1.c760 enc->enc_pic.ctx_buf.rec_luma_pitch = (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); in radeon_uvd_enc_ctx()
762 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); in radeon_uvd_enc_ctx()
764 enc->enc_pic.ctx_buf.rec_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe; in radeon_uvd_enc_ctx()
765 enc->enc_pic.ctx_buf.rec_chroma_pitch = enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe; in radeon_uvd_enc_ctx()
879 (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); in radeon_uvd_enc_encode_params_hevc()
881 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); in radeon_uvd_enc_encode_params_hevc()
883 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe; in radeon_uvd_enc_encode_params_hevc()
885 enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe; in radeon_uvd_enc_encode_params_hevc()
Dradeon_uvd_enc.c325 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in radeon_uvd_create_encoder()
327 : align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in radeon_uvd_create_encoder()
/third_party/mesa3d/src/amd/addrlib/src/core/
Daddrlib2.cpp903 else if ((pIn->bpe != 0) && in ComputeSlicePipeBankXor()
904 (pIn->bpe != 8) && in ComputeSlicePipeBankXor()
905 (pIn->bpe != 16) && in ComputeSlicePipeBankXor()
906 (pIn->bpe != 32) && in ComputeSlicePipeBankXor()
907 (pIn->bpe != 64) && in ComputeSlicePipeBankXor()
908 (pIn->bpe != 128)) in ComputeSlicePipeBankXor()
/third_party/python/Lib/concurrent/futures/
Dprocess.py446 bpe = BrokenProcessPool("A process in the process pool was "
450 bpe.__cause__ = _RemoteTraceback(
455 work_item.future.set_exception(bpe)
/third_party/mesa3d/src/amd/vulkan/
Dradv_image.c1289 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe; in radv_init_metadata()
1307 if (!surf->cmask_size || surf->cmask_offset || surf->bpe > 8 || image->info.levels > 1 || in radv_image_alloc_single_sample_cmask()
1504 image->planes[i].surface.bpe = vk_format_get_blocksize(format); in radv_image_reset_layout()
1507 if (image->planes[i].surface.bpe == 3) { in radv_image_reset_layout()
1508 image->planes[i].surface.bpe = 4; in radv_image_reset_layout()
1563 if (mod_info->pPlaneLayouts[plane].rowPitch % image->planes[plane].surface.bpe || in radv_image_create_layout()
1568 stride = mod_info->pPlaneLayouts[plane].rowPitch / image->planes[plane].surface.bpe; in radv_image_create_layout()
2282 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3; in radv_GetImageSubresourceLayout()
2287 assert(util_is_power_of_two_nonzero(surface->bpe)); in radv_GetImageSubresourceLayout()
2288 pLayout->rowPitch = pitch * surface->bpe; in radv_GetImageSubresourceLayout()
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Dradv_meta_dcc_retile.c64 nir_ssa_def *src = ac_nir_dcc_addr_from_coord(&b, &dev->physical_device->rad_info, surf->bpe, in build_dcc_retile_compute_shader()
69 &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation, in build_dcc_retile_compute_shader()
/third_party/mesa3d/src/amd/addrlib/src/
Daddrinterface.cpp868 UINT_32 bpe = 0; in ElemSize() local
874 bpe = pLib->GetBpe(format); in ElemSize()
877 return bpe; in ElemSize()
/third_party/gstreamer/gstplugins_good/gst/avi/
Dgstavidemux.c1245 guint16 bpe = 16; in gst_avi_demux_parse_superindex() local
1273 bpe = GST_READ_UINT16_LE (data) * 4; in gst_avi_demux_parse_superindex()
1280 if (num > G_MAXUINT32 >> 1 || bpe < 8) { in gst_avi_demux_parse_superindex()
1286 if (size < 24 + bpe * (i + 1)) in gst_avi_demux_parse_superindex()
1288 indexes[i] = GST_READ_UINT64_LE (&data[24 + bpe * i]); in gst_avi_demux_parse_superindex()
1314 num, bpe); in gst_avi_demux_parse_superindex()
1533 guint16 bpe; in gst_avi_demux_parse_subindex() local
1554 bpe = (data[2] & 0x01) ? 12 : 8; in gst_avi_demux_parse_subindex()
1555 if (GST_READ_UINT16_LE (data) != bpe / 4 || in gst_avi_demux_parse_subindex()
1561 bpe = GST_READ_UINT16_LE (data) * 4; in gst_avi_demux_parse_subindex()
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