Home
last modified time | relevance | path

Searched refs:constlen (Results 1 – 25 of 28) sorted by relevance

12

/third_party/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3_const.h71 assert(regid + sizedwords <= v->constlen * 4); in emit_const_asserts()
131 if (16 * v->constlen <= state->range[i].offset) in ir3_emit_constant_data()
137 size = MIN2(size, (16 * v->constlen) - state->range[i].offset); in ir3_emit_constant_data()
177 if (16 * v->constlen <= state->range[i].offset) in ir3_emit_user_consts()
183 size = MIN2(size, (16 * v->constlen) - state->range[i].offset); in ir3_emit_user_consts()
216 if (v->constlen > offset) { in ir3_emit_ubos()
250 assert(offset * 4 + params <= v->constlen * 4); in ir3_emit_ubos()
264 if (v->constlen > offset) { in ir3_emit_image_dims()
304 uint32_t size = MIN2(ARRAY_SIZE(dims), v->constlen * 4 - offset * 4); in ir3_emit_image_dims()
322 size = MIN2(size + base, v->constlen) - base; in ir3_emit_immediates()
[all …]
Dir3_gallium.c92 v->info.max_half_reg + 1, v->info.max_reg + 1, v->constlen, in dump_shader_info()
223 if (v->constlen > compiler->max_const_safe) { in create_initial_variants()
235 if (v->constlen > compiler->max_const_safe) { in create_initial_variants()
/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_program.c85 uint8_t constlen; member
107 assert(s[i].v->constlen % 4 == 0); in setup_stages()
108 s[i].constlen = s[i].v->constlen / 4; in setup_stages()
116 s[i].constlen = 0; in setup_stages()
143 s[VS].constlen = 66; in setup_stages()
144 s[FS].constlen = 128 - s[VS].constlen; in setup_stages()
148 s[FS].constoff = s[VS].constlen; in setup_stages()
246 A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen) | in fd4_program_emit()
251 A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s[FS].constlen) | in fd4_program_emit()
256 A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) | in fd4_program_emit()
[all …]
Dfd4_emit.c134 assert(dst_offset + num <= v->constlen * 4); in emit_const_ptrs()
/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_program.c156 constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0; in fd3_program_emit()
216 OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) | in fd3_program_emit()
219 OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) | in fd3_program_emit()
243 A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) | in fd3_program_emit()
245 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen - 1, 0))); in fd3_program_emit()
315 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) | in fd3_program_emit()
318 MAX2(fp->constlen - 1, 0)) | in fd3_program_emit()
323 MAX2(128, vp->constlen)) | in fd3_program_emit()
Dfd3_emit.c143 assert(dst_offset + num <= v->constlen * 4); in emit_const_ptrs()
/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_compute.c79 assert(v->constlen % 4 == 0); in cs_program_emit()
80 unsigned constlen = v->constlen / 4; in cs_program_emit() local
82 OUT_RING(ring, constlen); /* HLSQ_CS_CONSTLEN */ in cs_program_emit()
Dfd5_program.c158 uint8_t constlen; member
180 assert(s[i].v->constlen % 4 == 0); in setup_stages()
181 s[i].constlen = s[i].v->constlen / 4; in setup_stages()
189 s[i].constlen = 0; in setup_stages()
220 constoff += s[i].constlen; in setup_stages()
353 OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */ in fd5_program_emit()
357 OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */ in fd5_program_emit()
361 OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */ in fd5_program_emit()
365 OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */ in fd5_program_emit()
369 OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */ in fd5_program_emit()
/third_party/mesa3d/src/freedreno/ir3/
Dir3_shader.c169 v->constlen = MAX2(v->constlen, info->max_const + 1); in ir3_shader_assemble()
171 if (v->constlen > ir3_const_state(v)->offsets.driver_param) in ir3_shader_assemble()
179 v->constlen = align(v->constlen, 4); in ir3_shader_assemble()
561 constlens[i] = variants[i]->constlen; in ir3_trim_constlen()
734 so->info.max_half_reg + 1, so->info.max_reg + 1, so->constlen); in ir3_shader_disasm()
Ddisasm-a3xx.c133 DIV_ROUND_UP(ctx->stats->constlen, 4)); in print_stats()
439 ctx->stats->constlen = MAX2(ctx->stats->constlen, num); in disasm_field_cb()
Dir3_shader.h533 unsigned constlen; member
Dir3_compiler_nir.c802 ctx->so->constlen = in emit_intrinsic_load_ubo()
803 MAX2(ctx->so->constlen, in emit_intrinsic_load_ubo()
1665 ctx->so->constlen = in emit_intrinsic()
1666 MAX2(ctx->so->constlen, const_state->ubo_state.size / 16); in emit_intrinsic()
/third_party/mesa3d/src/freedreno/common/
Ddisasm.h46 int constlen; member
/third_party/mesa3d/src/freedreno/computerator/
Da6xx.c138 unsigned constlen = align(v->constlen, 4); in cs_program_emit() local
141 A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) | A6XX_HLSQ_CS_CNTL_ENABLED); in cs_program_emit()
273 size = MIN2(size + base, v->constlen) - base; in cs_const_emit()
Da4xx.c122 A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(v->constlen / 4)); in cs_program_emit()
215 size = MIN2(size + base, v->constlen) - base; in cs_const_emit()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_program.c285 debug_assert(state->vs->constlen >= state->bs->constlen); in setup_config_stateobj()
288 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(state->vs->constlen) | in setup_config_stateobj()
292 A6XX_HLSQ_HS_CNTL_CONSTLEN(state->hs->constlen))); in setup_config_stateobj()
295 A6XX_HLSQ_DS_CNTL_CONSTLEN(state->ds->constlen))); in setup_config_stateobj()
298 A6XX_HLSQ_GS_CNTL_CONSTLEN(state->gs->constlen))); in setup_config_stateobj()
300 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(state->fs->constlen) | in setup_config_stateobj()
Dfd6_compute.c54 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(v->constlen) | in cs_program_emit()
Dfd6_const.c134 int size = MIN2(1 + regid, v->constlen) - regid; in emit_stage_tess_consts()
/third_party/mesa3d/src/freedreno/.gitlab-ci/reference/
DdEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log814 - shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen
835 - shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen
892 - shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen
912 - shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen
1472 - shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen
1500 - shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen
Dglxgears-a420.log428 - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
447 - shaderdb: 0 last-baryf, 0 half, 1 full, 1 constlen
1028 - shaderdb: 0 last-baryf, 0 half, 4 full, 13 constlen
1063 - shaderdb: 5 last-baryf, 0 half, 1 full, 0 constlen
1646 - shaderdb: 0 last-baryf, 0 half, 5 full, 13 constlen
1680 - shaderdb: 5 last-baryf, 0 half, 1 full, 0 constlen
2065 - shaderdb: 0 last-baryf, 0 half, 5 full, 13 constlen
2097 - shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen
2445 - shaderdb: 0 last-baryf, 0 half, 4 full, 13 constlen
2480 - shaderdb: 5 last-baryf, 0 half, 1 full, 0 constlen
[all …]
/third_party/mesa3d/src/freedreno/decode/
Dpgmdump2.c394 full_regs, stats.constlen, stats.ss, stats.sy, 0, in decode_shader_descriptor_block()
/third_party/mesa3d/docs/relnotes/
D10.3.3.rst123 - freedreno/ir3: fix constlen with relative addressing
/third_party/mesa3d/src/freedreno/vulkan/
Dtu_pipeline.c405 size = MIN2(size + base, xs->constlen) - base; in tu_xs_get_immediates_packet_size_dwords()
448 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) | in tu6_emit_xs_config()
605 (16 * xs->constlen) - ubo_state->range[i].offset); in tu6_emit_xs()
868 size = (MIN2(size + base, consumer->constlen) - base) * 4; in tu6_emit_link_map()
2594 link->constlen = v->constlen; in tu_pipeline_set_linkage()
Dtu_cmd_buffer.c3307 size = MIN2(size, (16 * link->constlen) - state->range[i].offset); in tu6_user_consts_size()
3371 size = MIN2(size, (16 * link->constlen) - state->range[i].offset); in tu6_emit_user_consts()
3536 bool hs_uses_bo = pipeline->tess.hs_bo_regid < hs_link->constlen; in tu6_emit_tess_consts()
3540 bool ds_uses_bo = pipeline->tess.ds_bo_regid < ds_link->constlen; in tu6_emit_tess_consts()
4107 if (const_state->offsets.driver_param >= link->constlen) in vs_params_offset()
4432 if (link->constlen <= offset) in tu_emit_compute_driver_params()
4436 (link->constlen - offset) * 4); in tu_emit_compute_driver_params()
Dtu_private.h1170 uint32_t constlen; member

12